Area-efficient and ultra-low-power architecture of RSA processor for RFID

Presented is an area-efficient and ultra-low-power hardware architecture of a 1024-bit RSA processor using a modified Montgomery algorithm. Since RSA for RFID often offers authentication and data encryption, small area, low power and high speed are its final goal. Proposed is the following progress: 1. to improve the Montgomery algorithm including preprocessing and Montgomery multiplication; 2. to design an architecture by pipelining two parallel multiply-add units using two-port register files; 3. to provide low power design methods. The result is the lowest power architecture of an RSA processor. The design has been fabricated using SMIC 0.13 µm CMOS technology and the test results show that the proposal design is most suitable for the low power systems.