An FPGA implementation guide for some different types of serial–parallel multiplier structures

[1]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[2]  O. L. Macsorley.  High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.

[3]  Earl E. Swartzlander.  The Quasi-Serial Multiplier , 1973, IEEE Transactions on Computers.

[4]  Bruce A. Wooley,et al.  A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.

[5]  P. E. Blankenship.  Comments on "A Two's Complement Parallel Array Multiplication Algorithm" , 1974, IEEE Trans. Computers.

[6]  Ratan K. Guha,et al.  The Two's Complement Quasi-Serial Multiplier , 1975, IEEE Transactions on Computers.

[7]  R. Gnanasekaran,et al.  On a Bit-Serial Input and Bit-Serial Output Multiplier , 1983, IEEE Transactions on Computers.

[8]  Per-Erik Danielsson.  Serial/Parallel Convolvers , 1984, IEEE Transactions on Computers.

[9]  R. Gnanasekaran,et al.  A Fast Serial-Parallel Binary Multiplier , 1985, IEEE Transactions on Computers.

[10]  I-Chen Wu.  A Fast 1-D Serial-Parallel Systolic Multiplier , 1987, IEEE Trans. Computers.

[11]  Satnam Dlay,et al.  VLSI design for diminished-1 multiplication of integers modulo a Fermat number , 1988 .

[12]  Stamatis Vassiliadis,et al.  A General Proof for Overlapped Multiple-Bit Scanning Multiplications , 1989, IEEE Trans. Computers.

[13]  Homayoon Sam,et al.  A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations , 1990, IEEE Trans. Computers.

[14]  Barrie Hayes-Gill,et al.  Novel pipelined serial/parallel multiplier , 1990 .

[15]  Mile K. Stojcev,et al.  Pipelined serial/parallel multiplier with contraflowing data streams , 1991 .

[16]  Barrie Hayes-Gill,et al.  Novel cell architecture for bit level systolic arrays multiplication , 1991 .

[17]  F. El-Guibaly,et al.  Area-efficient diminished-1 multiplier for fermat number-theoretic transform , 1993 .

[18]  S. Sunder,et al.  Two's-complement fast serial-parallel multiplier , 1995 .

[19]  Khaled Elleithy,et al.  A systolic architecture for modulo multiplication , 1995 .

[20]  Andreas Antoniou,et al.  Area-efficient multipliers for digital signal processing applications , 1996 .

[21]  F. Rongen,et al.  A flexible compatible PCI interface for nuclear experiments , 1997 .