Buffer delay change in the presence of power and ground noise

Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.

[1]  Yaochao Yang,et al.  Design for velocity saturated, short-channel CMOS drivers with simultaneous switching noise and switching time considerations , 1996, IEEE J. Solid State Circuits.

[2]  Lawrence T. Pileggi,et al.  CMOS gate delay models for general RLC loading , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[3]  J. S. Neely,et al.  Interconnect and circuit modeling techniques for full-chip power supply noise analysis , 1998 .

[4]  A. Kahng,et al.  A new approach to simultaneous buffer insertion and wire sizing , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[5]  Ishiuchi,et al.  Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .

[6]  S. R. Vemuru.  Effects of simultaneous switching noise on the tapered buffer design , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Lawrence T. Pileggi,et al.  Modeling the "Effective capacitance" for the RC interconnect of CMOS gates , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Mark A. Franklin,et al.  Optimum buffer circuits for driving long uniform lines , 1991 .

[9]  K. Bowman,et al.  Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance , 2000, IEEE Journal of Solid-State Circuits.

[10]  Lawrence T. Pileggi,et al.  A Gate-Delay Model for High-Speed CMOS Circuits , 1994, 31st Design Automation Conference.

[11]  Malgorzata Marek-Sadowska,et al.  Coping with buffer delay change due to power and ground noise , 2002, DAC '02.

[12]  Charles J. Alpert,et al.  Buffer insertion for noise and delay optimization , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Oh-Kyong Kwon,et al.  An analytical model of simultaneous switching noise in CMOS systems , 2000 .

[14]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1995, ICCAD.

[15]  Asim J. Al-Khalili,et al.  Estimation of ground bounce effects on CMOS circuits , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[16]  Takayasu Sakurai,et al.  Delay analysis of series-connected MOSFET circuits , 1991 .

[17]  Resve A. Saleh,et al.  Clock skew verification in the presence of IR-drop in the powerdistribution network , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  P.D. Gross,et al.  Determination of worst-case aggressor alignment for delay calculation , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[19]  K.-H. Erhard,et al.  Topology optimization techniques for power/ground networks in VLSI , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[20]  Kjell O. Jeppson,et al.  CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Massoud Pedram,et al.  Analysis and optimization of ground bounce in digital CMOS circuits , 2000, Proceedings 2000 International Conference on Computer Design.