A 691 Mbps 1.392mm2 configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS

This paper presents a unified parallel radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems. A radix-16 decoding for both binary and duo-binary turbo codes is proposed to reduce complexity as well as critical path delay. In addition, the two distinct interleavers in the standards are implemented with low-complexity address generator and barrel shift networks. Furthermore, quad-bank memory partition facilitates parallel radix-16 decoding without address conflict. Fabricated in TSMC 65nm CMOS process, the ASIC attains 691Mbps throughput running at 512MHz and 5.5 iterations. For the 326.4Mbps LTE peak data rate, it consumes only 193mW at 0.9V supply voltage with unprecedented energy efficiency of 0.108nJ/bit/iteration.

[1]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[2]  Naresh R. Shanbhag,et al.  Area-efficient high-throughput MAP decoder architectures , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Cheng-Chi Wong,et al.  A 952MS/s Max-Log MAP Decoder Chip using Radix-4 × 4 ACS Architecture , 2006, 2006 IEEE Asian Solid-State Circuits Conference.

[4]  Brian K. Classon,et al.  ARP and QPP Interleavers for LTE Turbo Coding , 2008, 2008 IEEE Wireless Communications and Networking Conference.

[5]  Joseph R. Cavallaro,et al.  Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards , 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.

[6]  In-Cheol Park,et al.  A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[7]  Cheng-Chi Wong,et al.  A 188-size 2.1mm2 reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system , 2009, 2009 Symposium on VLSI Circuits.

[8]  Qiuting Huang,et al.  Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE , 2011, IEEE Journal of Solid-State Circuits.

[9]  Yuan-Hao Huang,et al.  A 6.6pJ/bit/iter radix-16 modified log-MAP decoder using two-stage ACS architecture , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[10]  Cheng-Hung Lin,et al.  A 0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards , 2011, 2011 International Symposium on Integrated Circuits.

[11]  Yannick Saouter,et al.  High speed low complexity radix-16 Max-Log-MAP SISO decoder , 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

[12]  Christoph Roth,et al.  A 1Gbps LTE-advanced turbo-decoder ASIC in 65nm CMOS , 2013, 2013 Symposium on VLSI Circuits.