Combinationally irredundant ISCAS-89 benchmark circuits

We describe a procedure to remove combinationally redundant faults from a sequential circuit. The procedure removes gates, primary inputs, primary outputs and flip-flops, such that the resulting circuit is equivalent to the original circuit (by the definition given in a previous work). We present experimental results of the application of this procedure to ISCAS-89 benchmark circuits. The resulting circuits are available through anonymous ftp from ftp.eng.uiowa.edu in directory "pub/reddy/irrckts".

[1]  Kozo Kinoshita,et al.  Removal of redundancy in logic circuits under classification of undetectable faults , 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

[2]  Yahiko Kambayashi,et al.  The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.

[3]  Miron Abramovici,et al.  Low-cost redundancy identification for combinational circuits , 1994, Proceedings of 7th International Conference on VLSI Design.

[4]  Premachandran R. Menon,et al.  Multi-level Logic Optimization By Implication Analysis , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[5]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[6]  Irith Pomeranz,et al.  On Synthesis-for-Testability of Combinational Logic Circuits , 1995, 32nd Design Automation Conference.

[7]  Wu-Tung Cheng,et al.  Gentest: an automatic test-generation system for sequential circuits , 1989, Computer.

[8]  Kewal K. Saluja,et al.  Fast test generation for sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[9]  Kwang-Ting Cheng,et al.  Redundancy removal for sequential circuits without reset states , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Irith Pomeranz,et al.  Classification of Faults in Synchronous Sequential Circuits , 1993, IEEE Trans. Computers.

[11]  Michael H. Schulz,et al.  Advanced automatic test pattern generation and redundancy identification techniques , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[12]  Irith Pomeranz,et al.  On achieving complete testability of synchronous sequential circuits with synchronizing sequences , 1994, Proceedings., International Test Conference.

[13]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[14]  Fabio Somenzi,et al.  Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Kwang-Ting Cheng,et al.  Multi-level logic optimization by redundancy addition and removal , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[16]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .