A production worthy, copper CMP technology has been successfully developed on a multi-platen CMP system. The System consists of three polish platens, each of which is equipped with an optical endpoint detection system. The process consists of three steps with different polish slurries, and is designed to polish copper with a tantalum based barrier, and to achieve good defect performance. Patterned test wafers were processed and characterized to investigate the effect of overpolish, feature size and pattern density. Both electrical testing and various physical measurement techniques have been extensively used for the characterization. It is concluded that dishing and erosion start t o develop when the polishing reaches the barrier. The amount of dishing and erosion for each test structure depend primarily on the pattern itself and the amount of overpolishing, and secondarily on CMP consumable and process parameters. Essential to achieve a consistent chip interconnect parametric performance are: an optimized Cu CMP process, a set of interconnect layout design rules compatible with the Cu CMP capability, and equally important or more so, a robust CMP endpoint detection system.