Buffering Carbon Nanotube Interconnects Considering Inductive Effects

While copper interconnect scaling is approaching its fundamental physical limit, increasing wire resistivity and delay have greatly limited the circuit miniaturization. The emerging carbon nanotube...

[1]  Yehea I. Ismail,et al.  Signal waveform characterization in RLC trees , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[2]  Design optimization of high frequency op amp using 32 nm CNFET , 2010, International Conference on Electrical & Computer Engineering (ICECE 2010).

[3]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1996 .

[4]  P. J. Burke.  An RF circuit model for carbon nanotubes , 2003 .

[5]  P. Burke.  Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes , 2002 .

[6]  E. Campbell,et al.  A Three-Terminal Carbon Nanorelay , 2004 .

[7]  Charles J. Alpert,et al.  Wire segmenting for improved buffer insertion , 1997, DAC.

[8]  M. Radosavljevic,et al.  High-field electrical transport and breakdown in bundles of single-wall carbon nanotubes , 2001 .

[9]  Y. Massoud,et al.  On the Optimal Design, Performance, and Reliability of Future Carbon Nanotube-Based Interconnect Solutions , 2008, IEEE Transactions on Electron Devices.

[10]  P. Ajayan,et al.  Reliability and current carrying capacity of carbon nanotubes , 2001 .

[11]  Kaustav Banerjee,et al.  Are carbon nanotubes the future of VLSI interconnections? , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[12]  C. Alpert,et al.  Fast algorithms for slew constrained minimum cost buffering , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  G. Duesberg,et al.  Carbon nanotubes for interconnect applications , 2002, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[14]  H. Wong,et al.  Assembly and Electrical Characterization of Multiwall Carbon Nanotube Interconnects , 2008, IEEE Transactions on Nanotechnology.

[15]  K. Banerjee,et al.  Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects , 2008, IEEE Transactions on Electron Devices.

[16]  Louis Scheffer.  CAD Implications of New Interconnect Technologies , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[17]  C. Xu,et al.  Graphene nano-ribbon (GNR) interconnects: A genuine contender or a delusive dream? , 2008, 2008 IEEE International Electron Devices Meeting.

[18]  H. Gokturk,et al.  Electrical properties of ideal carbon nanotubes , 2005, 5th IEEE Conference on Nanotechnology, 2005..

[19]  P. McEuen,et al.  Single-walled carbon nanotube electronics , 2002 .

[20]  E. Anderson,et al.  Scanned probe microscopy of electronic transport in carbon nanotubes. , 2000, Physical review letters.

[21]  C. Schönenberger,et al.  Interference and Interaction in multi-wall carbon nanotubes , 1999, cond-mat/9905144.

[22]  K. Banerjee,et al.  High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design , 2009, IEEE Transactions on Electron Devices.

[23]  N. Vallepalli,et al.  A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply , 2005, IEEE Journal of Solid-State Circuits.

[24]  S. Datta.  Electrical resistance: an atomistic view , 2004, cond-mat/0408319.

[25]  Kaustav Banerjee,et al.  Performance analysis of carbon nanotube interconnects for VLSI applications , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[26]  Shiyan Hu,et al.  Buffering Single-Walled Carbon Nanotubes Bundle Interconnects for Timing Optimization , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[27]  Hai Wei,et al.  Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes , 2011, IEEE Transactions on Nanotechnology.

[28]  Nishant Patil,et al.  Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits , 2008, 2008 Design, Automation and Test in Europe.

[29]  Weiping Shi,et al.  A fast algorithm for optimal buffer insertion , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.