A Binary Counter Based on Stacking and Sorting

Binary counters are widely used as essential building blocks for varieties of circuit operations, especially for fast multipliers. In this paper, a 7:3 counter design is proposed, which uses 3- and 4-bit stackers to shift the “1” from one side to the other and then finds the “1” in the specified position by accurate sorting. Compared with previous designs, this counter reduces the number of XOR gates and curtails the critical path.

[1]  Graham A. Jullien,et al.  A New Design Technique for Column Compression Multipliers , 1995, IEEE Trans. Computers.

[2]  Ieee Circuits,et al.  IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  M. Mehta,et al.  High-speed multiplier design using multi-input counter and compressor circuits , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

[4]  Adly T. Fam,et al.  Fast Binary Counters Based on Symmetric Stacking , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Earl E. Swartzlander A review of large parallel counter designs , 2004, IEEE Computer Society Annual Symposium on VLSI.