An Interface with Two-Phase Delay-Insensitive Global Communication for GALS Systems

Complex digital circuits today are implemented in UDSM (Ultra Deep-Sub-micron) MOS technology. These circuits are designed in the Systems-on-Chip (SoC) style, operating with multiple clocks due to UDSM_MOS technology. An interesting style for SoC design with multiple clocks is the GALS (Globally Asynchronous, Locally Synchronous) paradigm. As the UDSM_MOS technology causes large variations in PVT (processes, voltage, and temperature), which leads to uncertainties in wires delays, therefore, communication between locally synchronous modules is an obstacle in high-performance design, especially when it comes to long wires. In this article, we propose an interface for point-to-point GALS systems insensitive to the latency of communication wires. This robustness is achieved by communicating the encoded data in the delay-insensitive (DI) style in the LEDR (Level-encoded 2-phase Dual-Rail) code. The proposed interface uses a unique port controller to perform DI communication between locally synchronous modules, which reduces latency and area compared to other interfaces based on port controllers. A comparison with the ports controllers responsible for the communication between the four modules of four wrappers found in the literature shows that the proposed port controller leads to an average reduction in latency of 61.4% compared with the communication ports of these four wrappers.

[1]  Florian Huemer,et al.  Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication , 2018, 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

[2]  Florian Huemer,et al.  A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols , 2015, 2015 Austrian Workshop on Microelectronics.

[3]  Jean-Michel Chabloz,et al.  Globally-Ratiochronous, Locally-Synchronous Systems , 2012 .

[4]  David Bol,et al.  Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic , 2009, ISLPED.

[5]  Akarsh Reddy Ravi.  GLOBALLY-ASYNCHRONOUS, LOCALLY-SYNCHRONOUS WRAPPER CONFIGURATIONS FOR POINT-TO-POINT AND MULTI-POINT DATA COMMUNICATION , 2004 .

[6]  Hossein Pedram,et al.  Globally asynchronous locally synchronous wrapper circuit based on clock gating , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[7]  Jonas Carlsson.  Studies on asynchronous communication ports for GALS systems , 2005 .

[8]  Daniel D. Gajski.  Principles of Digital Design , 1996 .

[9]  Fernando Gehm Moraes,et al.  SCAFFI: An intrachip FPGA asynchronous interface based on hard macros , 2007, 2007 25th International Conference on Computer Design.

[10]  James C. Ellenbogen,et al.  Overview of nanoelectronic devices , 1997, Proc. IEEE.

[11]  David L. Dill,et al.  Efficient self-timing with level-encoded 2-phase dual-rail (LEDR) , 1991 .

[12]  Hubert Kaeslin,et al.  Globally-asynchronous locally-synchronous architectures for VLSI systems , 2008 .

[13]  Florian Huemer,et al.  Advanced Delay-Insensitive 4-Phase Protocols , 2018, 2018 Austrochip Workshop on Microelectronics (Austrochip).

[14]  Duarte L. Oliveira,et al.  An Asynchronous Interface with Robust Control for Globally-Asynchronous Locally- Synchronous Systems , 2013 .

[15]  Kenneth Y. Yun,et al.  Pausible clocking-based heterogeneous systems , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Frank K. Gürkaynak.  GALS system design: side channel attack secure cryptographic accelerators , 2006 .

[17]  Tiago Curtinhas,et al.  FPGA Implementation of Low-Latency Robust Asynchronous Interfaces for GALS Systems , 2018, 2018 IEEE XXV International Conference on Electronics, Electrical Engineering and Computing (INTERCON).

[18]  Florian Huemer,et al.  Novel Approaches for Efficient Delay-Insensitive Communication , 2019 .

[19]  Eckhard Grass,et al.  System integration by request-driven GALS design , 2006 .

[20]  Steven M. Nowick,et al.  An error-correcting unordered code and hardware support for robust asynchronous global communication , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[21]  Alexandre Yakovlev,et al.  Advances in asynchronous logic: From principles to GALS & NoC, recent industry applications, and commercial CAD tools , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[22]  Fernando Gehm Moraes,et al.  A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines , 2011, IEEE Design & Test of Computers.

[23]  Vazgen Melikyan,et al.  Analysis of the impact of metastability phenomenon on the latency and power consumption of synchronizer circuits , 2016, 2016 IEEE East-West Design & Test Symposium (EWDTS).

[24]  Claude Thibeault,et al.  Asynchronous component implementation methodology for GALS design in FPGAs , 2009, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.

[25]  Shahriar Mirabbasi,et al.  System-on-Chip: Reuse and Integration , 2006, Proceedings of the IEEE.

[26]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[27]  Alain J. Martin,et al.  Asynchronous Techniques for System-on-Chip Design , 2006, Proceedings of the IEEE.

[28]  Luciano Lavagno,et al.  Coping with the variability of combinational logic delays , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[29]  Guy Lemieux,et al.  A Survey and Taxonomy of GALS Design Styles , 2007, IEEE Design & Test of Computers.