Reliability characterization of a commercial TaOx-based ReRAM

We present results of endurance and retention characterization for one of the first commercially available TaOx-based resistive memory chip in room and higher temperature environments. Data retention of the memory chip shows activation energy of 1.13eV and demonstrates an 85°C 10-year data retention even after 250,000 programming cycles. The combined program and read errors were in the range of 10-7 to 10-5 and the memory chip withstood 106 program cycles at 125°C. Overall, the reliability of this commercial resistive memory chip compares well with flash memory.

[1]  Ru Huang,et al.  Total Ionizing Dose (TID) Effects on $\hbox{TaO}_{x}$ -Based Resistance Change Memory , 2011, IEEE Transactions on Electron Devices.

[2]  M. Pasotti,et al.  Power efficient charge pump in deep submicron standard CMOS technology , 2003, Proceedings of the 27th European Solid-State Circuits Conference.

[3]  Kinam Kim,et al.  A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O(5-x)/TaO(2-x) bilayer structures. , 2011, Nature materials.

[4]  James A. Bain,et al.  Comparison of electric field dependent activation energy for electroformation in TaOx and TiOx based RRAMs , 2013, 2013 IEEE International Integrated Reliability Workshop Final Report.

[5]  Z. Wei,et al.  Demonstration of high-density ReRAM ensuring 10-year retention at 85°C based on a newly developed reliability model , 2011, 2011 International Electron Devices Meeting.

[6]  S. M. Dalton,et al.  Initial Assessment of the Effects of Radiation on the Electrical Characteristics of ${\rm TaO}_{\rm x}$ Memristive Memories , 2012, IEEE Transactions on Nuclear Science.

[7]  Hisashi Shima,et al.  Resistive Random Access Memory (ReRAM) Based on Metal Oxides , 2010, Proceedings of the IEEE.

[8]  U. Böttger,et al.  Beyond von Neumann—logic operations in passive crossbar arrays alongside memory operations , 2012, Nanotechnology.

[9]  Gregory S. Snider,et al.  ‘Memristive’ switches enable ‘stateful’ logic operations via material implication , 2010, Nature.

[10]  Onur Mutlu,et al.  Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  Tsutomu Yoshihara,et al.  A 3.3 V-only 16 Mb DINOR flash memory , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[12]  T. Nagumo,et al.  High thermal robust ReRAM with a new method for suppressing read disturb , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[13]  Jim Hutchby,et al.  Assessment of the Potential & Maturity of Selected Emerging Research Memory Technologies Workshop & ERD/ERM Working Group Meeting (April 6-7, 2010) , 2010 .

[14]  Z. Wei,et al.  Conductive filament scaling of TaOx bipolar ReRAM for long retention with low current operation , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[15]  Dong Wu,et al.  Investigation of TID degradation of high voltage circuits in flash memory , 2013, 2013 IEEE International Integrated Reliability Workshop Final Report.

[16]  Allan H. Johnston,et al.  Radiation effects on advanced flash memories , 1999 .