Low-cost port allocation scheme for minimizing deflections in bufferless on-chip networks

The bufferless deflection routing is recently emerged as a promising approach for improving energy efficiency of on-chip networks. In this on-chip router design, input buffers are removed, and instead deflection (i.e. misrouting) is used to resolve contention among arriving packets. However, to be effective, this concept needs to be supported with an efficient port allocation scheme which should minimize deflections when forwarding input packets to output ports. This paper presents a new port allocation scheme for bufferless on-chip routers. The proposed solution follows the distributed structure of the port allocator introduced in CHIPPER router, which is composed of four arbiter blocks arranged in a two-stage permutation network, but changes the way each arbiter behaves. Instead of randomized priority-based arbitration policy, the proposed scheme routes packets through the permutation network by choosing configuration which minimizes deflection at output of each arbiter block. The performance analysis against baseline CHIPPER router shows an advantage for our proposal of up to 41% in terms of network throughput.