Charge sharing based 10T SRAM for low-power

CAD tools are provided by IDEC Korea. First two authors are supported by HEC Pakistan. Partial funding was provided by Samsung Electronics Korea.

[1]  Anantha Chandrakasan,et al.  Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access , 2013, IEEE Journal of Solid-State Circuits.

[2]  Jun Zhou,et al.  Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[4]  Mohammad Sharifkhani,et al.  A Subthreshold Symmetric SRAM Cell With High Read Stability , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Meng-Fan Chang,et al.  A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications , 2011, IEEE Journal of Solid-State Circuits.

[7]  Zhiyu Liu,et al.  Characterization of a Novel Nine-Transistor SRAM Cell , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Ulrich Rückert,et al.  A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control , 2013, IEEE Journal of Solid-State Circuits.

[9]  Dhiraj K. Pradhan,et al.  A single ended 6T SRAM cell design for ultra-low-voltage applications , 2008, IEICE Electron. Express.

[10]  C. M. R. Prabhu,et al.  Low-power fast (LPF) SRAM cell for write/read operation , 2011, IEICE Electron. Express.

[11]  Manoj Sachdev,et al.  CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test , 2008 .