A BIST Circuit for IDDQ Tests

An IDDQ test time reduction method is proposed which is suitable for BIST approaches in this paper. Also, a BIST circuit for IDDQ tests based on the method is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performances are evaluated by SPICE simulation. The results show us that IDDQ test time can be reduced by using the test circuit.

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