Critical Dimension and Real-Time Temperature Control for Warped Wafers

Abstract In this paper, we present the experimental results on Critical Dimension (CD) control via real-time temperature control for warped wafers. As opposed to run-to-run control where information from the previous wafer or batch is used for control of the current wafer or batch, the approach here is real-time and make use of current information for control of the current wafer CD. In this paper we demonstrate that real-time control of the post-exposure bake temperature to give nonuniform temperature distribution across the warped wafer can reduce CD nonuniformity across the wafer.

[1]  A. Adeyeye,et al.  Swing effects in alternating phase shift mask lithography: Implications of low σ illumination , 2006 .

[2]  Peter Dress,et al.  Global critical dimension uniformity improvement for mask fabrication with negative-tone chemically amplified resists by zone-controlled postexposure bake , 2004 .

[3]  Lay Lay Lee,et al.  Real-time predictive control of photoresist film thickness uniformity , 2002 .

[4]  A. Tay,et al.  Integrated bake/chill module with in situ temperature measurement for photoresist processing , 2004, IEEE Transactions on Semiconductor Manufacturing.

[5]  Michel Marcel Jose Decre,et al.  Cover Layer Technology for the High-Numerical-Aperture Digital Video Recording System , 2000 .

[6]  Roxann L. Engelstad,et al.  Inter- and intramembrane resist critical dimension uniformity across a SCALPEL mask , 2000 .

[7]  A. Yen,et al.  Thin-film optimization strategy in high numerical aperture optical lithography, part 2: applications to ArF , 2005 .

[8]  Charles D. Schaper,et al.  Programmable thermal processing module for semiconductor substrates , 2004, IEEE Transactions on Control Systems Technology.

[9]  Natarajan Ramanan,et al.  Simulation studies and experimental verification of the performance of a lithocell combination bake-chill station , 2004 .

[10]  I. C. Ume,et al.  Warpage measurement of large area multitilted silicon substrates at various processing conditions , 2000 .

[11]  Burn Jeng Lin,et al.  Thin-film optimization strategy in high numerical aperture optical lithography, part 1: principles , 2005 .

[12]  Weng Khuen Ho,et al.  An In Situ Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography , 2007, IEEE Transactions on Semiconductor Manufacturing.

[13]  Scott Daniel Hector,et al.  Critical dimension control in optical lithography , 2003 .

[14]  A. Tay,et al.  In situ fault detection of wafer warpage in microlithography , 2004, IEEE Transactions on Semiconductor Manufacturing.

[15]  Koji Kaneyama,et al.  Optimizing CD uniformity by total PEB cycle temperature control on track equipment , 2002, SPIE Advanced Lithography.

[16]  Costas J. Spanos,et al.  Characterizing post-exposure bake processing for transient- and steady-state conditions in the context of critical dimension control , 2002, SPIE Advanced Lithography.

[17]  Daniel E. Miller,et al.  ArF processing of 90-nm design rule lithography achieved through enhanced thermal processing , 2006, SPIE Advanced Lithography.