Implementation of Inverse Transform in H.264/AVC Decoder Using Coded Block Pattern

In this paper, we propose the architecture of Inverse Transform in H.264/AVC Decoder to reduce the processing cycle and power consumption by using the CBP(Coded Block Pattern). We also propose the internal buffer instead of using external RAM to reduce the external memory access. By proposed methods, we can reduce average 10% processing cycle. Our proposed Inverse Transform is verified by Verilog HDL and with the 0.35 um process. This architecture can be operated by Max. 100㎒.