Optimum State Assignment for Synchronous Sequential Circuits

The problem of encoding the internal states of synchronous sequential switching circuits so as to minimize the combinational network cost is treated. Cost is defined as the number of AND-OR inputs required in the two-level implementation of each memory element input equation separately ( i.e., the cost is not reduced initially by the existence of common terms between equations). An algorithm has been developed that considers implicitly all distinct state-assignment schemes for a given state table, thus ensuring that the state assignment that results in the least "cost" combinational network is selected. Since any optimum state-assignment scheme is dependent on the type of memory element, the algorithm is designed for use with J-K flip-flop memory elements because of their wide use and versatility.

[1]  H. A. Curtis.  Illustration of design methods for power reduction in logical systems , 1965 .

[2]  Douglas B. Armstrong.  On the Efficient Assignment of Internal Codes to Sequential Machines , 1962, IRE Trans. Electron. Comput..

[3]  Stephen H. Unger,et al.  A Note on the Number of Internal Variable Assignments for Sequential Switching Circuits , 1959, IRE Trans. Electron. Comput..

[4]  Charles A. Harlow,et al.  On the Structure of Realizations Using Flip-Flop Memory Elements , 1967, Inf. Control..

[5]  H. Allen Curtis.  Multiple Reduction of Variable Dependency of Sequential Machines , 1962, JACM.

[6]  Wayne A. Davis.  An Approach to the Assignment of Input Codes , 1967, IEEE Trans. Electron. Comput..

[7]  Richard Edwin Stearns,et al.  On the State Assignment Problem for Sequential Machines II , 1961, IRE Trans. Electron. Comput..

[8]  Peter Weiner,et al.  Optimization of Reduced Dependencies for Synchronous Sequential Machines , 1967, IEEE Trans. Electron. Comput..

[9]  Richard M. Karp,et al.  Some Techniques of State Assignment for Synchronous Sequential Machines , 1964, IEEE Trans. Electron. Comput..

[10]  Charles A. Harlow,et al.  On the structure of sequential machine realizations , 1967 .

[11]  Hwa C. Torng,et al.  An Algorithm for Finding Secondary Assignments of Synchronous Sequential Circuits , 1968, IEEE Transactions on Computers.

[12]  Douglas B. Armstrong,et al.  A Programmed Algorithm for Assigning Internal Codes to Sequential Machines , 1962, IRE Trans. Electron. Comput..

[13]  H. Allen Curtis.  Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part II , 1970, IEEE Transactions on Computers.

[14]  Edward J. McCluskey,et al.  The Coding of Internal States of Sequential Circuits , 1964, IEEE Trans. Electron. Comput..

[15]  H. C. Torng.  Introduction to the logical design of switching systems , 1964 .

[16]  Juris Hartmanis,et al.  On the State Assignment Problem for Sequential Machines. I , 1961, IRE Trans. Electron. Comput..

[17]  Edward J. McCluskey,et al.  Introduction to the theory of switching circuits , 1965 .

[18]  Montgomery Phister,et al.  Logical design of digital computers , 1958, Digital design and applications.

[19]  H. Allen Curtis,et al.  Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part I , 1969, IEEE Transactions on Computers.

[20]  Peter Weiner,et al.  On the Number of Distinct State Assignments for Synchronous Sequential Machines , 1967, IEEE Trans. Electron. Comput..