Design of Low Power CMOS VCO Having Low Phase Noise

The growing demand for high-speed wireless connectivity has accelerated the development of data-centric third-generation (3G) services, particularly the wireless local area network (WLAN) communications protocols such as the Institute of Electrical and Electronics Engineers (IEEE) standard 802.11a and the European Telecommunications Standardization Institute (ETSI) standard HiperLAN2. To support the increasingly faster data rates and to combat the less favorable propagation conditions at higher carrier frequencies, these standards employ the more complex modulation scheme of orthogonal frequency division multiplexing (OFDM). With OFDM, the carrier is subdivided into several individually modulated orthogonal subcarriers, all of which are simultaneously transmitted (1)-(4). However, a higher data rate is often accompanied by more sensitivity to phase errors for a particular modulation scheme. This increased sensitivity is inevitably translated into more stringent phase noise requirements for the voltage-controlled oscillator (VCO). The VCO is an integral and critical part of a phase-locked loop (PLL) or a frequency synthesizer often found in the transceivers of modern communications systems.

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