Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS
暂无分享,去创建一个
D. Schmitt-Landsiedel | P. Seegebrecht | R. Thewes | R. Brederlow | C. Pacha | K. von Arnim | J. Berthold | B. Martin
[1] Mi-Chang Chang,et al. Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era , 2003 .
[2] S. Odanaka,et al. Narrow-width effects of shallow trench-isolated CMOS with n/sup +/-polysilicon gate , 1989 .
[3] Andrew R. Brown,et al. Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .
[4] Y. Sonobe,et al. Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics , 2004, IEEE Transactions on Electron Devices.