Scaling towards 35 nm gate length CMOS

We report 35 nm gate length planar CMOS transistors with aggressively scaled gate equivalent oxide thickness (EOT). A nitride/oxynitride (N/O) stack was used as gate dielectric with EOT ranging from 12 /spl Aring/ down to 7 /spl Aring/. The impact of gate scaling on transistor performance, gate tunneling leakage, short-channel effect, and channel carrier mobility is investigated. Excellent control of short-channel effect is achieved for sub-50 nm gate length devices. CV/I delays of 0.89 ps for n-MOSFET and 1.8 ps for p-MOSFET are demonstrated at a supply voltage of 0.85 V.