A low complexity FEC design for DAB

In this paper, because of FEC block hardware size in DAB system, is considered to have the benefit of efficient usage. A Proposed architecture has only 8 GF-multipliers and 4 GF-adders in RS coder, 2 RAM(128) and 4 RAM(256) in convolutional interleaver. We have designed FEC block for DAB system and have implemented on Altera-FPGA chip(FLEX 10K) successfully.