论文信息 - Impact of on-chip process variations performance on MCML [MOS current mode logic]

Impact of on-chip process variations performance on MCML [MOS current mode logic]

The effect of on-chip process variations on MOS current mode logic (MCML) performance is explored. A closed form expression for the noise-margin is derived. On-chip process variations are shown to set the lower limit for the power dissipation of an MCML family.

S. Bruma

[1] J. Lohstroh,et al. Worst-case static noise margin criteria for logic circuits and their mathematical equivalence , 1983, IEEE Journal of Solid-State Circuits.

[2] Masayuki Mizuno,et al. A GHz MOS adaptive pipeline technique using MOS current-mode logic , 1996, IEEE J. Solid State Circuits.

[3] Jan M. Rabaey,et al. MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[4] J. Lohstroh. Static and dynamic noise margins of logic circuits , 1979 .

[5] Masakazu Yamashina,et al. An MOS Current Mode Logic (MCML) Circuit for Low-Power Sub-GHz Processors , 1992 .

[6] Robert G. Meyer,et al. Analysis and Design of Analog Integrated Circuits , 1993 .

[7] Evert Seevinck,et al. Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's , 1991 .

[8] Mohamed I. Elmasry,et al. Self-timed MOS current mode logic for digital applications , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).