Architectural Optimization Methods for Control-Dominated Machines

We are building the Princeton University Behavioral Synthesis System (PUBSS) as a testbed for high-level synthesis methods. Our research in high-level synthesis is guided by two principles: concentration on control-dominated machines and development of optimization methods for partially-specified architectures.

[1]  S. Hayati,et al.  Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions , 1989, 26th ACM/IEEE Design Automation Conference.

[2]  Wayne H. Wolf,et al.  The FSM network model for behavioral synthesis of control-dominated machines , 1990, 27th ACM/IEEE Design Automation Conference.

[3]  John W. Tukey,et al.  Exploratory Data Analysis. , 1979 .

[4]  Kurt Keutzer,et al.  An automata-theoretic approach to behavioral equivalence , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[5]  Giovanni De Micheli,et al.  Relative scheduling under timing constraints , 1991, DAC '90.

[6]  V. Berstis.  The V compiler: automatic hardware design , 1989, IEEE Design & Test of Computers.

[7]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[8]  Randy H. Katz,et al.  A new interface specification methodology and its application to transducer synthesis , 1988 .

[9]  Daniel D. Gajski,et al.  Flow Graph Representation , 1986, DAC 1986.

[10]  Joe D. Warren,et al.  The program dependence graph and its use in optimization , 1987, TOPL.

[11]  John A. Nestor,et al.  SALSA: a new approach to scheduling with timing constraints , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  A. Sangiovanni-Vincentelli,et al.  The TimberWolf placement and routing package , 1985, IEEE Journal of Solid-State Circuits.

[13]  D W Knapp,et al.  A Data Structure for VLSI Synthesis and Verification , 1983 .

[14]  Mark N. Wegman,et al.  An efficient method of computing static single assignment form , 1989, POPL '89.

[15]  E. F. Girczyc,et al.  HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis , 1986, 23rd ACM/IEEE Design Automation Conference.

[16]  Edmund M. Clarke,et al.  A language for compositional specification and verification of finite state hardware controllers , 1991 .

[17]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.

[18]  Giovanni De Micheli,et al.  HERCULES-a system for high-level synthesis , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[19]  Raul Camposano,et al.  Path-based scheduling for synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  W. M. Wonham,et al.  The control of discrete event systems , 1989 .

[21]  W. Wolf.  An algorithm for nearly-minimal collapsing of finite-state machine networks , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[22]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Howard Trickey,et al.  Flamel: A High-Level Hardware Compiler , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  P. Six,et al.  Cathedral-II: A Silicon Compiler for Digital Signal Processing , 1986, IEEE Design & Test of Computers.

[25]  Daniel Barbará,et al.  Spanner: A Tool for the Specification, Analysis, and Evaluation of Protocols , 1987, IEEE Transactions on Software Engineering.

[26]  Donald E. Thomas,et al.  Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench , 1989 .