Breaking the GOP / Watt Barrier with EDGE Architectures

Achieving excellent power/performance ratios is easy for processor designs that have sufficiently low performance needs. The techniques traditionally used to extract higher levels of performance from RISC or CISC architectures, however, have either exacerbated power limitations or placed an undue burden on the programmer. In this paper, we describe how Explicit Data Graph Execution (EDGE) architectures have the potential to offer both high performance and high programmer productivity while achieving a high performance/power ratio.