A framework for synthesis and verification of analog systems

In this paper we present a framework for synthesis and verification of analog systems. The famework is composed of a synthesis module and a verification module. Synthesis is in the form of architectural synthesis from behavioral specifications, and verification in the form of behavioral simulation of the synthesized architectures. The synthesis and verification techniques are implemented in an object-oriented paradigm, using anopen systems approach which enables customizing the target CAD framework. An Architecture Specification Language (ASL) is defined using the C++ programming language constructs. The integrated synthesis-verification framework provides for design space exploration enabling trade-offs in architectural as well as circuit technology characteristics. This paper focuses on the framework and implementation aspects of the architectural synthesis and verification methodology.

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