An industrial fault injection platform for soft-error dependability analysis and hardening of complex system-on-a-chip

This paper presents a fault injection platform that is currently developed and used to perform soft-error dependability analysis and hardening of complex SoCs1. Primarily, it is oriented toward safety analysis, safety requirement conformance testing and hardening of complex SoCs. This platform makes use of clusters of hardware emulation resources available for SoC verification to achieve massive faults injection capabilities. It is able to distribute fault injection campaigns across multiple heterogeneous emulation platforms to achieve high fault coverage. It is able to virtually handle almost any circuit size and is designed to support all kind of designs. We present the first results obtained on a small design, the Leon2 IP, on which exhaustive fault injection have been performed.

[1]  F. Bezerra,et al.  Two Complementary Approaches for Studying the Effects of SEUs on Digital Processors , 2007, IEEE Transactions on Nuclear Science.

[2]  Johan Karlsson,et al.  Comparison of Physical and Software-Implemented Fault Injection Techniques , 2003, IEEE Trans. Computers.

[3]  Mehdi Baradaran Tahoori,et al.  Estimating Error Propagation Probabilities with Bounded Variances , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[4]  C. Lopez-Ongil,et al.  Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation , 2007, IEEE Transactions on Nuclear Science.

[5]  Jean Arlat,et al.  Coverage Estimation Methods for Stratified Fault Injection , 1999, IEEE Trans. Computers.

[6]  Bharat L. Bhuva,et al.  Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor , 2000 .

[7]  Jean Arlat,et al.  Estimators for Fault Tolerance Coverage Evaluation , 1995, IEEE Trans. Computers.

[8]  G. Gasiot,et al.  Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering , 2007, IEEE Transactions on Nuclear Science.

[9]  Afshin Abdollahi.  Probabilistic decision diagrams for exact probabilistic analysis , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[10]  Sanjay J. Patel,et al.  Examining ACE analysis reliability estimates using fault-injection , 2007, ISCA '07.

[11]  Alfredo Benso,et al.  A Functional Verification based Fault Injection Environment , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[12]  James E. Bartlett,et al.  Organizational research: Determining appropriate sample size in survey research , 2001 .

[13]  Sandeep K. Shukla,et al.  Scalable techniques and tools for reliability analysis of large circuits , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[14]  Kartik Mohanram,et al.  Accurate and scalable reliability analysis of logic circuits , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[15]  Sandeep K. Shukla,et al.  Reliability Analysis of Large Circuits Using Scalable Techniques and Tools , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Pradip Bose,et al.  Phaser: Phased methodology for modeling the system-level effects of soft errors , 2008, IBM J. Res. Dev..

[17]  Massimo Violante,et al.  Fault Injection-based Reliability Evaluation of SoPCs , 2006, Eleventh IEEE European Test Symposium (ETS'06).

[18]  J.-F. Naviner,et al.  Efficient computation of logic circuits reliability based on Probabilistic Transfer Matrix , 2008, 2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era.

[19]  C. Lopez-Ongil,et al.  A Unified Environment for Fault Injection at Any Design Level Based on Emulation , 2007, IEEE Transactions on Nuclear Science.