Automatic synthesis of application-specific programmable processors

As witnessed by their recent rapid market growth, reconfigurable multi-functional data paths are an attractive alternative to both fully programmable and fully custom hardware platforms. We present a methodology for behavioral synthesis of an important and large class of reconfigurable data path designs, application specific programmable processors (ASPPs). ASPPs are data paths which provide efficient implementation for any of N functional specifications assuming that only one will be executed at any given time. The synthesis of ASPP designs imposes numerous new tasks on behavioral synthesis tools. We address bundling of applications, where n control-data flow graphs are bundled into at most m groups so that the area overhead is minimized, and all throughput constraints are satisfied. A variety of application specific constraints such as manufacturing cost minimization and risk reduction constraints are incorporated with application bundling. Task preemption is a critical enabling mechanism in a variety of multi-task real-time application scenarios. On preemption, data in the register files must be preserved in order for the task to be resumed. This entails extra memory to preserve the context and additional clock cycles to save and restore the context. We propose techniques and algorithms to incorporate micro-preemption constraints during ASPP synthesis. Specifically, we develop a controller based scheme to preclude preemption related performance degradation, techniques to minimize the context switch overhead, and algorithms to insert and refine preemption points in scheduled task graphs subject to preemption latency constraints. This on-the-fly task preemption distinguishes ASPPs from other adaptive computing architectures. Using the architectural flexibility provided by behavioral synthesis scheduling and resource allocation, we develop a novel approach for permanent fault-tolerance. This technique combines the behavioral synthesis-based flexibility provided by each of multiple functionalities with judicious application-to-faulty-unit assignment either to maximize the permanent fault-tolerance of such ASPPs (resource constrained fault-tolerant ASPP synthesis) or to guarantee that the ASPP remains operational in the presence of all possible k-unit faults (fault-tolerance constrained ASPP synthesis). We demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of industrial-strength designs.