Partial Core Encryption for Performance-Efficient Test of SOCs
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[1] Prab Varma,et al. A unifying methodology for intellectual property and custom logic testing , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[2] Yervant Zorian,et al. Testing embedded-core based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[3] Sujit Dey,et al. A low overhead design for testability and test generation technique for core-based systems-on-a-chip , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Sarita Thakar,et al. On the generation of test patterns for combinational circuits , 1993 .
[5] Nur A. Touba,et al. Using Partial Isolation Rings to Test Core-Based Designs , 1997, IEEE Des. Test Comput..
[6] David Bryan,et al. Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.
[7] Kaushik De,et al. Test methodology for embedded cores which protects intellectual property , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).