Single Phase Dynamic CMOS POS PLA

This paper presents two types of single phase dynamic CMOS NOR-NOR PLA. The PLAs use triggered decoders and charge sharing resulting in high speed circuits with low power dissipation. By using triggered decoders, ground switches can be eliminated, thus making this new design much faster and dissipate less power than single phase conventional CMOS PLAs. By using charge-sharing, a cascading AND gate can be implemented. The two types of 2.0 pm CMOS PLA were simulated and their resulting delay-times were much less than that of a conventional single phase CMOS PLA. The POS PLA using triggered 1-bit decoders (three-valued logic) and the POS PLA using triggered 2-bit decoders are respectively, 1.8 and 2.2 times faster than the conventional PLA. For a typical PLA with 48 input minterms and 8 output minterms, and they have respectively, 2.2 and 3.4 times less power dissipation than the conventional PLA.