Vertical Channel Capacitor-less One-Transistor DRAMs with a pass-way Trench for improving Retention Time

In this paper, we propose a capacitor-less 1T-DRAM structure with the pass-way trench for improving the Retention Time (RT). We have improved the device fabrication process to form the pass-way trench of the structure which combines the Vertical Channel and the Gate-All-Around structure (PTVCT). The memory operation and its attractive performance in terms of programming window, retention time, and writing time are investigated. The pass-way trench improves programming window and retention time of the structure in comparison to conventional structure.