Beyond performance: secure and fair memory management for multiple systems on a chip

Developments in VLSI technologies create the possibility of hosting several independent (sub) systems in a single chip. There is a need to share a number of resources, especially off-chip resources, which creates new constraints in the design process. Although performance is still a key constraint, sharing implies that secure access to those resources and QoS guarantees are needed. In this paper, an architecture is presented that achieves the goals listed above. The Embedded Hardware Manager acts as a middleware between the applications and the resources, taking the role of resource manager and security agent. The results show that it can prevent resource misuse and undue information peeking or even altering while maintaining individual QoS guarantees. At the same time, high performance is still achieved.

[1]  D. Verkest,et al.  System-level performance optimization of the data queueing memory management in high-speed network processors , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[2]  Sally A. McKee,et al.  Dynamic Access Ordering for Streamed Computations , 2000, IEEE Trans. Computers.

[3]  Zhao Zhang,et al.  A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality , 2000, MICRO 33.

[4]  John W. Lockwood,et al.  Reprogrammable network packet processing on the field programmable port extender (FPX) , 2001, FPGA '01.

[5]  William J. Dally,et al.  Memory access scheduling , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[6]  F. Gharsalli,et al.  Automatic generation of embedded memory wrapper for multiprocessor SoC , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[7]  Seth Copen Goldstein,et al.  Mobile Memory: Improving memory locality in very large reconfigurable fabrics , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[8]  C. Green,et al.  ANALYZING AND IMPLEMENTING SDRAM AND SGRAM CONTROLLERS , 1998 .

[9]  Sally A. McKee,et al.  Hardware Support for Dynamic Access Ordering: Performance of Some Design Options , 1993 .

[10]  Erik Brunvand,et al.  Impulse: building a smarter memory controller , 1999, Proceedings Fifth International Symposium on High-Performance Computer Architecture.