Modeling of charge trapping induced threshold-voltage instability in high-/spl kappa/ gate dielectric FETs

The authors have developed a distributed tunneling model to investigate the threshold-voltage instability induced by charge trapping in field-effect transistors (FETs) using high-/spl kappa/ gate dielectric materials. The charge trapping dynamics in the high-/spl kappa/ layer are modeled based on a rate equation, which is self-consistently incorporated into device-level simulations. The model is used to simulate pulsed operation of HfO/sub 2/ based n-type FETs; good agreement is obtained with pulsed measurements including the dependence of the threshold-voltage shift on pulse heights and durations. The trap-energy-level shift due to the polaron effect is found to be critical to model the pulse-height dependence of the threshold-voltage shift.

[1]  J. L. Lentz,et al.  An improved electron and hole mobility model for general purpose device simulation , 1997 .

[2]  E. Cartier,et al.  Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-κ insulator: The role of remote phonon scattering , 2001 .

[3]  E. Montroll,et al.  Anomalous transit-time dispersion in amorphous solids , 1975 .

[4]  L. Colombo,et al.  Characterization and comparison of the charge trapping in HfSiON and HfO/sub 2/ gate dielectrics , 2003, IEEE International Electron Devices Meeting 2003.

[5]  N. Mott,et al.  Electronic Processes In Non-Crystalline Materials , 1940 .

[6]  D. Hisamoto,et al.  Unified mobility model for high-/spl kappa/ gate stacks [MISFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[7]  K. Matsuzawa,et al.  A unified simulation of Schottky and ohmic contacts , 2000 .

[8]  X. Garros,et al.  Characterization and modeling of hysteresis phenomena in high K dielectrics , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[9]  T. Chikyow,et al.  Physical model of BTI, TDDB and SILC in HfO/sub 2/-based high-k gate dielectrics , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[10]  J. Robertson.  High dielectric constant oxides , 2004 .

[11]  Massimo V. Fischetti,et al.  Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks , 2003 .

[12]  L. Pantisano,et al.  Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics , 2003, IEEE Electron Device Letters.