Low temperature fluxless technology for ultra-fine pitch and large devices flip-chip bonding

For heterogeneous materials assemblies, the thermal expansion mismatch between the chip and the substrate represents the most important bottleneck for fine pitch and large devices. Generally numerical stress analysis of flip chip ball grid array (BGA) package assemblies focus on the reliability of solder interconnects during thermal cycling. Here, we conduct finite element modeling to evaluate the degradation occurring during the flip chip process itself. Residual strain due to CTE mismatch appears in the peripheral connections during the cool down to room temperature after solidification of the microbumps. Moreover the assembly presents a residual warpage caused by CTE mismatch which can compromise the component use. We calculate residual strain and warpage to evaluate the thermo-mechanical limits of soldering method for ultra-high density interconnects. In order to overcome this problem, a room temperature interconnection technology appears as a good solution to prevent the assembly from residual strain and warpage. This paper presents a new patented flip-chip bonding method which is being investigated for the next generation of microelectronic packaging. Instead of soldering, electrical connections are performed by the insertion of conductive micro-tips in ductile bumps, at low temperature without flux