Introduction The supply voltage scaling in DRAMs for power reduction and to maintain the device reliability puts the most serious constr,int on the conventional one-transistor cell( 1Tcell) design. Even if employing a three dimensional capacitor structure with high dielectric constant material such as TazO5, it is difficult to continue scaling the 1T-cell having sufficient storage capacitance for entering giga-bit era. To overcome this limitation, we have proposed a complementary gain(CG) cell which can operates under a supply voltage below 1V without increasing storage capacitance[ 11. In this paper, super low voltage operation of the CG cell is analytically investigated. The optimum operating conditions, immunity to noise on bitline and speed are discussed.