Fault pattern oriented defect diagnosis for memories

Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experiences of the FA engineer is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new development flow that enables the product to reach a profitable yield level as soon as possible. Demand in methodologies that allow FA automation thus increases rapidly in recent years. This paper proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit-level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main contribution of the paper is thus a methodology and procedure for accelerating FA and yield optimization for semiconductor memories.

[1]  L. J. Bock,et al.  Paper 2. , 1973, The Australian journal of physiotherapy.

[2]  Said Hamdioui,et al.  An experimental analysis of spot defects in SRAMs: realistic fault models and tests , 2000, Proceedings of the Ninth Asian Test Symposium.

[3]  A.J. van de Goor,et al.  RAM diagnostic tests , 1996, IEEE International Workshop on Memory Technology, Design and Testing,.

[4]  Cheng-Wen Wu,et al.  Error catch and analysis for semiconductor memories using March tests , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[5]  David Y. Lepejian,et al.  Using Electrical Bitmap Results from Embedded Memory to Enhance Yield , 2001, IEEE Des. Test Comput..

[6]  Ad J. van de Goor,et al.  Generating march tests automatically , 1994, Proceedings., International Test Conference.

[7]  Jin-Fu Li,et al.  A built-in self-test and self-diagnosis scheme for embedded SRAM , 2000, Proceedings of the Ninth Asian Test Symposium.

[8]  Cheng-Wen Wu,et al.  Simulation-based test algorithm generation for random access memories , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[9]  Wojciech Maly,et al.  Enabling embedded memory diagnosis via test response compression , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[10]  F. Joel Ferguson,et al.  Cache RAM inductive fault analysis with fab defect modeling , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[11]  Frans P. M. Beenker,et al.  Fault modeling and test algorithm development for static random access memories , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[12]  Mahmud Adnan,et al.  An Overview of Advanced Failure Analysis Techniques for Pentium and Pentium Pro Microprocessors 1 An Overview of Advanced Failure Analysis Techniques for Pentium and Pentium Pro Microprocessors , 1998 .

[13]  Ad J. van de Goor,et al.  Semiconductor manufacturing process monitoring using built-in self-test for embedded memories , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[14]  Rosa Rodríguez-Montañés,et al.  Resistance characterization for weak open defects , 2002, IEEE Design & Test of Computers.

[15]  M.A. Merino,et al.  SmartBit/sup TM/: bitmap to defect correlation software for yield improvement , 2000, 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072).

[16]  Yervant Zorian,et al.  A March-based fault location algorithm for static random access memories , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

[17]  Ad J. van de Goor,et al.  Defining SRAM resistive defects and their simulation stimuli , 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

[18]  Y. Zorian.  Embedding infrastructure IP for SOC yield improvement , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).