Circuits for resilient systems

Timing and functional failures caused by process, voltage and temperature (PVT) variations pose major challenges to achieving energy-efficient performance in multi-core & many-core processor designs in nanoscale CMOS. Radiation-induced soft errors and aging-induced degradations limit power, performance and reliability. These impacts are further aggravated in the Near-Threshold Voltage (NTV) operating regime where energy efficiency peaks. We will discuss opportunities for variation-tolerant logic and memory design that enable robust operation in nanoscale CMOS. Adaptation and reconfiguration, combined with efficient error detection and response schemes, can mitigate impacts of dynamic variations.