Sustainable DVFS-Enabled Multi-Core Architectures with On-Chip Wireless Links
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[1] Somayeh Sardashti,et al. The gem5 simulator , 2011, CARN.
[2] Li Shang,et al. Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links , 2002, IEEE Computer Architecture Letters.
[3] Partha Pratim Pande,et al. Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects , 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.
[4] Radu Marculescu,et al. Variation-adaptive feedback control for networks-on-chip with multiple clock domains , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[5] Jason Howard. A 48-core IA-32 processor with on-die message-passing and DVFS in 45nm CMOS , 2010, 2010 IEEE Asian Solid-State Circuits Conference.
[6] Radu Marculescu,et al. Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip , 2012, JETC.
[7] Christof Teuscher,et al. Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems , 2011, IEEE Transactions on Computers.
[8] Saurabh Dighe,et al. A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling , 2011, IEEE Journal of Solid-State Circuits.
[9] P. Burke,et al. Quantitative theory of nanowire and nanotube antenna performance , 2004, IEEE Transactions on Nanotechnology.
[10] Diana Marculescu,et al. Speed and voltage selection for GALS systems based on voltage/frequency islands , 2005, ASP-DAC.
[11] Partha Pratim Pande,et al. Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
[12] Saurabh Dighe,et al. Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[13] Luca P. Carloni,et al. Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors , 2008, IEEE Transactions on Computers.
[14] Meeta Sharma Gupta,et al. System level analysis of fast, per-core DVFS using on-chip switching regulators , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[15] Chih-Ming Hung,et al. Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters , 2002, IEEE J. Solid State Circuits.
[16] David Z. Pan,et al. A Voltage-Frequency Island aware energy optimization framework for networks-on-chip , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.
[17] Radu Marculescu,et al. "It's a small world after all": NoC performance optimization via long-range link insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[18] Aaron Stein,et al. Hot Carrier Electroluminescence from a Single Carbon Nanotube , 2004 .
[19] Jason Cong,et al. A scalable micro wireless interconnect structure for CMPs , 2009, MobiCom '09.
[20] G. Hanson,et al. On the Applicability of the Surface Impedance Integral Equation for Optical and Near Infrared Copper Dipole Antennas , 2006, IEEE Transactions on Antennas and Propagation.
[21] K. Kempa,et al. Carbon Nanotubes as Optical Antennae , 2007 .
[22] W. Yin,et al. Performance Prediction of Carbon Nanotube Bundle Dipole Antennas , 2008, IEEE Transactions on Nanotechnology.
[23] Yi Wang,et al. SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip , 2008, IEEE Transactions on Computers.
[24] David W. Matolak,et al. iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture , 2011, 2011 IEEE 19th Annual Symposium on High Performance Interconnects.
[25] Constantino Tsallis,et al. Optimization by Simulated Annealing: Recent Progress , 1995 .
[26] A. Biberman,et al. Ultrahigh-Bandwidth Silicon Photonic Nanowire Waveguides for On-Chip Networks , 2008, IEEE Photonics Technology Letters.
[27] David Z. Pan,et al. A voltage-frequency island aware energy optimization framework for networks-on-chip , 2008, ICCAD 2008.
[28] Margaret Martonosi,et al. Techniques for Multicore Thermal Management: Classification and New Exploration , 2006, ISCA 2006.
[29] H. Lhermet,et al. An Asynchronous Power Aware and Adaptive NoC Based Circuit , 2009, IEEE Journal of Solid-State Circuits.
[30] N.K. Jha,et al. Toward Ideal On-Chip Communication Using Express Virtual Channels , 2008, IEEE Micro.
[31] Niraj K. Jha,et al. Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[32] Kevin Skadron,et al. Temperature-aware microarchitecture , 2003, ISCA '03.
[33] Radu Marculescu,et al. Quantum-Like Effects in Network-on-Chip Buffers Behavior , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[34] Jung Ho Ahn,et al. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[35] Anoop Gupta,et al. The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.
[36] P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .
[37] Natalie D. Enright Jerger,et al. Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[38] Y. Zhou,et al. Design and Fabrication of Microheaters for Localized Carbon Nanotube Growth , 2008, 2008 8th IEEE Conference on Nanotechnology.
[39] Christian Bienia,et al. Benchmarking modern multiprocessors , 2011 .
[40] T. Marinis,et al. Wafer level vacuum packaging of MEMS sensors , 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..