Design Tools for3DMixedModePlacement
暂无分享,去创建一个
Zhuoyuan Li | Vijay Pitchumani | Xianlong Hong | Jinian Bian | Haixia Yan | Jinian Bian | Zhuoyuan Li | Xianlong Hong | V. Pitchumani | Haixia Yan
[1] Shashi Shekhar,et al. Multilevel hypergraph partitioning: application in VLSI domain , 1997, DAC.
[2] Qiang Zhou,et al. Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design , 2005, ICCSA.
[3] Martin D. F. Wong,et al. Floorplanning for 3-D VLSI design , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[4] Sachin Sapatnekar,et al. Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach , 2003, ICCAD 2003.
[5] Joseph R. Shinnerl,et al. An Enhanced Multilevel Algorithm for Circuit Placement , 2003, ICCAD 2003.
[6] Charles J. Alpert,et al. The ISPD98 circuit benchmark suite , 1998, ISPD '98.