Pipelining-based tradeoffs for hardware/software codesign of multimedia systems

In the last years, multimedia systems are present in an ever increasing number of applications. A software implementation often can not satisfy system timing constraints. This problem can be solved by adding specific hardware to the system. Lately, it has been developed some design methodologies for this type of hardware/software systems. Our research group have developed a hardware/software codesign environment named GACSYS (GAC's Codesign System) for designing this type of systems. In this article, we present our Hw/Sw partitioning tool. Main contribution of our tool is the following: it supports process-level pipelining and takes into account system power consumption. Thus, system designer can explore the design space to make new latency, area and power trade-offs.

[1]  Ahmed Amine Jerraya,et al.  Interactive system-level partitioning with PARTIF , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[2]  M. Garey.  Johnson: computers and intractability: a guide to the theory of np- completeness (freeman , 1979 .

[3]  Frank Vahid,et al.  A system-design methodology: executable-specification refinement , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[4]  Wayne Wolf,et al.  Process partitioning for distributed embedded systems , 1996, Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96.

[5]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[6]  John P. Knight,et al.  Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level , 1995, 32nd Design Automation Conference.

[7]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[8]  Peter Duzy,et al.  The Synthesis Approach to Digital System Design , 1992 .

[9]  Xiaobo Sharon Hu,et al.  Configuration-level hardware/software partitioning for real-time embedded systems , 1994, CODES.

[10]  P. Eles,et al.  VHDL system-level specification and partitioning in a hardware/software co-synthesis environment , 1994, Third International Workshop on Hardware/Software Codesign.

[11]  Donald E. Thomas,et al.  Architectural partitioning for system level synthesis of integrated circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Donatella Sciuto,et al.  Partitioning and Exploration Strategies in the TOSCA Co-Design Flow , 1996, CODES.

[13]  H. Veit,et al.  CASTLE: an interactive environment for HW-SW co-design , 1994, Third International Workshop on Hardware/Software Codesign.

[14]  Wayne H. Wolf,et al.  Process Partitioning for Distributed Embedded Systems , 1996, CODES.

[15]  C. Carreras,et al.  A co-design methodology based on formal specification and high-level estimation , 1996, Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96.

[16]  Frank Vahid,et al.  Towards a model for hardware and software functional partitioning , 1996, Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96.

[17]  Luciano Lavagno,et al.  Hardware-Software Co-Design of Embedded Systems , 1997 .

[18]  Edward A. Lee,et al.  A hardware-software codesign methodology for DSP applications , 1993, IEEE Design & Test of Computers.

[19]  Reiner W. Hartenstein,et al.  Two-level partitioning of image processing algorithms for the parallel Map-oriented Machine , 1996, Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96.

[20]  Ahmed Amine Jerraya,et al.  Synthesis Steps and Design Models for Codesign , 1995, Computer.

[21]  Frank Vahid,et al.  Clustering for improved system-level functional partitioning , 1995, Proceedings of the Eighth International Symposium on System Synthesis.

[22]  J. P. Castellano.  Lenguaje de especificación y particionado hardware/software para codiseño de sistemas , 1999 .

[23]  Jörg Henkel,et al.  Hardware-software cosynthesis for microcontrollers , 1993, IEEE Design & Test of Computers.

[24]  C. Reeves.  Modern heuristic techniques for combinatorial problems , 1993 .

[25]  Armin Bender.  MILP based task mapping for heterogeneous multiprocessor systems , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[26]  Axel Jantsch,et al.  Hardware/software partitioning and minimizing memory interface traffic , 1994, EURO-DAC '94.

[27]  Niraj K. Jha,et al.  Behavioral synthesis for low power , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[28]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[29]  Edward A. Lee,et al.  A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem , 1994, CODES.

[30]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[31]  Jan Madsen,et al.  PACE: a dynamic programming algorithm for hardware/software partitioning , 1996, Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96.

[32]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[33]  E. Macii,et al.  High-level Power Modeling, Estimation, And Optimization , 1997, Proceedings of the 34th Design Automation Conference.

[34]  Peter Marwedel,et al.  Hardware/software partitioning using integer programming , 1996, Proceedings ED&TC European Design and Test Conference.

[35]  J. P. Castellano,et al.  Intermediate representations of concurrent VHDL-based specifications , 1997, PDP.

[36]  Dorit S. Hochbaum,et al.  Approximation Algorithms for NP-Hard Problems , 1996 .

[37]  Luciano Lavagno,et al.  Hardware-software codesign of embedded systems , 1994, IEEE Micro.