An Integral Equation Hybrid Method for the Impedance Calculation of the Grid Power Distribution Network With an Arbitrary Shape
暂无分享,去创建一个
Shiyou Yang | Yanbin Yang | Li Ding | Guoping Zou | Xingchang Wei | Weiying Ding | Wei-Ying Ding | Shiyou Yang | Xingchang Wei | Yanbin Yang | L. Ding | Guoping Zou
[1] Minjia Xu,et al. The development of a closed-form expression for the input impedance of power-return plane structures , 2003 .
[2] Ghyslain Gagnon,et al. On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[3] Taigon Song,et al. PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[4] Xing-Chang Wei,et al. Modeling of the Simultaneous Switching Noise in High Speed Electronic Circuit with the Integral Equation Method and Vector Fitting Method , 2011, IEEE Transactions on Magnetics.
[6] Leung Tsang,et al. Erratum: Application of the Foldy‐Lax multiple scattering method to the analysis of vias in ball grid arrays and interior layers of printed circuit boards , 2007 .
[7] Xing-Chang Wei,et al. A Novel Hybrid Analytical Method for Impedance Calculation of Power and Ground Planes , 2013, IEEE Transactions on Electromagnetic Compatibility.
[8] Xing-Chang Wei,et al. Modeling and Design of Electromagnetic Compatibility for High-Speed Printed Circuit Boards and Packaging , 2017 .
[9] Junho Lee,et al. Interposer Power Distribution Network (PDN) Modeling Using a Segmentation Method for 3-D ICs With TSVs , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[10] Wei-Ying Ding,et al. A Closed-Form Solution for the Impedance Calculation of Grid Power Distribution Network , 2017, IEEE Transactions on Electromagnetic Compatibility.
[11] Joungho Kim,et al. Power distribution networks for system-on-package: status and challenges , 2004, IEEE Transactions on Advanced Packaging.
[12] Madhavan Swaminathan,et al. On-Chip Power-Grid Simulation Using Latency Insertion Method , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.