HAL: A High-Speed Logic Simulation Machine

The architecture of a very-high-speed logic simulation machine (HAL), which can simulate up to one-half million gates and 2M-byte memory chips at a 5 ms clock speed, is described. This machine makes it possible to debug the total system¿CPU, main memory, cache memory and control storage¿before the actual machine is fabricated. HAL employs parallel and pipeline processing, and event-driven, block-level logic simulation. The prototype system for a 32-processor system has been constructed and is now in use as a tool for large mainframe computer development. HAL is more than a thousand times faster than existing software logic simulators.

[1]  N. Koike,et al.  High speed logic simulation machine , 1983 .

[2]  Eric Paul Kronstadt,et al.  Design and implementation of a software simulation engine , 1983 .

[3]  Gregory F. Pfister,et al.  Software Support for the Yorktown Simulation Engine , 1982, 19th Design Automation Conference.

[4]  Larry N. Dunn.  IBM'S Engineering Design System Support for VLSI Design and Verification , 1984, IEEE Design & Test of Computers.

[5]  Gregory Francis Pfister,et al.  The Yorktown Simulation Engine: Introduction , 1982, DAC 1982.

[6]  Tom Blank,et al.  A Survey of Hardware Accelerators Used in Computer-Aided Design , 1984, IEEE Design & Test of Computers.

[7]  Nobuhiko Koike,et al.  HAL; A Block Level Hardware Logic Simulator , 1983, 20th Design Automation Conference Proceedings.

[8]  Anthony P. Ambler,et al.  ULTIMATE: A Hardware Logic Simulation Engine , 1984, 21st Design Automation Conference Proceedings.

[9]  M.M. Denneau.  The Yorktown Simulation Engine , 1982, 19th Design Automation Conference.

[10]  P. R. Menon,et al.  A logic simulation machine , 1982, ISCA.

[11]  P. R. Menon,et al.  Special-purpose computer for logic simulation using distributed processing , 1982, The Bell System Technical Journal.