Defect tolerance for nanocomputer architecture

Defect tolerant architectures will be mandatory for building economical and cheap computing systems with billions of devices of nanometer dimension because it will contain significant number of defects due to statistical variations. The basic idea behind a defect tolerant custom configurable system is to build the system out of partially perfect components, detect the defects and configure the available good resources using software. In this paper we discuss implications of defect tolerance on power, area, delay and other relevant parameters for computing architectures. The additional requirement of a scalable configuration mechanism, redundant components and detection scheme necessitates extra burden on the interconnect to sustain it. Through back-of-envelope calculations using a priori wire length estimation and intuitive arguments we will illustrate the hidden cost of supporting such an architecture.

[1]  W. R. Heller,et al.  Wirability-designing wiring space for chips and chip packages , 1984, IEEE Design & Test of Computers.

[2]  W. Donath.  Equivalence of memory to Random Logic , 1974 .

[3]  Roy L. Russo,et al.  On a Pin Versus Block Relationship For Partitions of Logic Graphs , 1971, IEEE Transactions on Computers.

[4]  Michael Feuer.  Connectivity of Random Logic , 1982, IEEE Transactions on Computers.

[5]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[6]  Dirk Stroobandt,et al.  A Priori Wire Length Estimates for Digital Design , 2001 .

[7]  Paul G. Spirakis,et al.  On the Fault Tolerance of Fat-Trees , 1997, Euro-Par.

[8]  Abbas El Gamal,et al.  Two-dimensional stochastic model for interconnections in master-slice integrated circuits , 1981 .

[9]  William E. Donath,et al.  Placement and average interconnection lengths of computer logic , 1979 .

[10]  Shankar Krishnamoorthy,et al.  Estimating routing congestion using probabilistic analysis , 2001, ISPD '01.

[11]  Yen-Tai Lai,et al.  Hierarchical interconnection structures for field programmable gate arrays , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[13]  Majid Sarrafzadeh,et al.  Congestion estimation during top-down placement , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Dennis Sylvester,et al.  2003 International Workshop on System-Level Interconnect Prediction (SLIP) , 2002 .

[15]  Richard J. Carter,et al.  Exploring architectures for volume visualization on the Teramac custom computer , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[16]  Shankar Krishnamoorthy,et al.  Estimating routing congestion using probabilistic analysis , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[18]  Malgorzata Marek-Sadowska,et al.  Interconnect complexity-aware FPGA placement using Rent's rule , 2001, SLIP '01.

[19]  Glenn H. Chapman,et al.  Defect and Fault Tolerance in VLSI Systems , 2003 .

[20]  Dhanistha Panyasak,et al.  Circuits , 1995, Annals of the New York Academy of Sciences.

[21]  Gregory S. Snider,et al.  A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology , 1998 .

[22]  Richard J. Carter,et al.  Teramac-configurable custom computing , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[23]  Jan M. Van Campenhout,et al.  Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle , 1999, VLSI Design.