An Algorithm for the Optimization of Pipelined Recursive Digital Filters

In very large-scale integration (VLSI) implementations of infinite-impulse response (IIR) filters, the maximal achievable sampling rate is limited by the ratio between the number of delay elements and the latency of the arithmetic operations in the critical recursive loop. One alternative to increase the maximal sampling rate is to use the so-called pipelined IIR filters, where some first coefficients in the filter denominator are forced to be zero, increasing the number of delays in the critical loop. Typically, pipelined filters are generated from conventional IIR filters with the aid of proper transformations. The purpose of this paper is twofold. First, an efficient optimization technique is proposed for improving the performance of the transformed pipelined filters. Second, the latency is decreased by optimizing the filter coefficients, with the aid of another algorithm, to have very simple finite-precision forms, thereby increasing the sampling rate even further. The advantages of the proposed algorithms are illustrated by means of an example taken from the literature. Index Terms — Optimization, pipelined recursive digital filters, IIR filters, multiplierless design, common subexpression elimination, VLSI implementations, clustered look-ahead transformation.

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