A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers
暂无分享,去创建一个
[1] Eugenio Culurciello,et al. Second generation of high dynamic range, arbitrated digital imager , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[2] Eugenio Culurciello,et al. A comparative study of access topologies for chip-level address-event communication channels , 2003, IEEE Trans. Neural Networks.
[3] Amine Bermak,et al. A PWM DPS with pixel-level reconfigurable 4/8-bit counter/SRAM , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[4] M.J.M. Pelgrom,et al. Matching properties of MOS transistors , 1989 .
[5] V. Villamayor,et al. Monolithic integration of spectrally selective uncooled lead selenide detectors for low cost applications , 2003 .
[6] L. McIlrath. A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion , 2001, IEEE J. Solid State Circuits.
[7] E. Vittoz,et al. An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications , 1995 .