Error Sequence Analysis

With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, such as the transition fault model and the path-delay model, have been used to aid delay defect detection. However, these models are not efficient for small-delay defect coverage or for test pattern generation time. Error sequence analysis utilizes the order in which the errors occur during a frequency sweep of a transition test to identify small- delay defects that may escape the same test applied in the conventional way. Moreover, it can detect such defects even in the presence of inter-die process variations, such as lot-to-lot and wafer-to-wafer process variation. In addition, error sequence analysis is very effective in separating devices with delay defects from devices that have failed due to process variation.

[1]  Srinivas Patil,et al.  Broad-side delay test , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Haihua Yan,et al.  Evaluating the effectiveness of detecting delay defects in the slack interval: a simulation study , 2004 .

[3]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[4]  Edward J. McCluskey,et al.  Very-low-voltage testing for weak CMOS logic ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[5]  Edward J. McCluskey,et al.  Delay defect screening using process monitor structures , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[6]  Srinivas Patil,et al.  On broad-side delay test , 1994, Proceedings of IEEE VLSI Test Symposium.

[7]  Phillip J. Nigh.  Achieving quality levels of 100 DPM: it's possible... but roll up your sleeves and be prepared to do some work , 2004 .

[8]  Michael S. Hsiao,et al.  ALAPTF: a new transition fault model and the ATPG algorithm , 2004, 2004 International Conferce on Test.

[9]  W. Robert Daasch,et al.  Silicon evaluation of longest path avoidance testing for small delay defects , 2007, 2007 IEEE International Test Conference.

[10]  Haihua Yan,et al.  Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[11]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[12]  Ananta K. Majhi,et al.  On hazard-free patterns for fine-delay fault testing , 2004 .

[13]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[14]  Jing Wang,et al.  K longest paths per gate (KLPG) test generation for scan-based sequential circuits , 2004 .

[15]  D. M. H. Walker,et al.  An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit , 2003, International Test Conference, 2003. Proceedings. ITC 2003..