Compiling for reconfigurable computing: A survey

Reconfigurable computing platforms offer the promise of substantially accelerating computations through the concurrent nature of hardware structures and the ability of these architectures for hardware customization. Effectively programming such reconfigurable architectures, however, is an extremely cumbersome and error-prone process, as it requires programmers to assume the role of hardware designers while mastering hardware description languages, thus limiting the acceptance and dissemination of this promising technology. To address this problem, researchers have developed numerous approaches at both the programming languages as well as the compilation levels, to offer high-level programming abstractions that would allow programmers to easily map applications to reconfigurable architectures. This survey describes the major research efforts on compilation techniques for reconfigurable computing architectures. The survey focuses on efforts that map computations written in imperative programming languages to reconfigurable architectures and identifies the main compilation and synthesis techniques used in this mapping.

[1]  Bill Salefski,et al.  Re-configurable computing in wireless , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[2]  Richard Sharp,et al.  A Higher-Level Language for Hardware Synthesis , 2001, CHARME.

[3]  Rajeev Barua,et al.  Compiler Support for Scalable and Efficient Memory Systems , 2001, IEEE Trans. Computers.

[4]  Horácio C. Neto,et al.  Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines , 2001, FPL.

[5]  Vivek Sarkar,et al.  Space-time scheduling of instruction-level parallelism on a raw machine , 1998, ASPLOS VIII.

[6]  Donald E. Thomas,et al.  Synthesis by Delayed Binding of Decisions , 1985, 22nd ACM/IEEE Design Automation Conference.

[7]  Ranga Vemuri,et al.  An integrated temporal partioning and partial reconfiguration technique for design latency improvement , 2000, DATE '00.

[8]  Dan Zuras,et al.  Integer multiplication and division on the HP precision architecture , 1987, IEEE Trans. Computers.

[9]  Carl Ebeling,et al.  Specifying and compiling applications for RaPiD , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[10]  Yuichiro Shibata,et al.  Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware , 2000, FPL.

[11]  Ranga Vemuri,et al.  Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[12]  John Wawrzynek,et al.  Adapting software pipelining for reconfigurable computing , 2000, CASES '00.

[13]  Herman Schmit,et al.  Behavioral synthesis for FPGA-based computing , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[14]  Pedro C. Diniz,et al.  Evaluation of code generation strategies for scalar replaced codes in fine-grain configurable architectures , 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

[15]  Alok N. Choudhary,et al.  FPGA hardware synthesis from MATLAB , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[16]  Jan Hoogerbrugge,et al.  ConCISe: a compiler-driven CPLD-based instruction set accelerator , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[17]  Mary W. Hall,et al.  Custom data layout for memory parallelism , 2004, International Symposium on Code Generation and Optimization, 2004. CGO 2004..

[18]  Wonyong Sung,et al.  AUTOSCALER for C: an optimizing floating-point to integer C program converter for fixed-point digital signal processors , 2000 .

[19]  Ranga Vemuri,et al.  Combined temporal partitioning and scheduling for reconfigurable architectures , 1999, Optics East.

[20]  Richard J. Carter,et al.  Teramac configurable custom computer , 1995, Optics East.

[21]  Bruce A. Draper,et al.  Mapping a Single Assignment Programming Language to Reconfigurable Systems , 2002, The Journal of Supercomputing.

[22]  Steven A. Guccione,et al.  The XC6200DS development system , 1997, FPL.

[23]  Scott Hauck,et al.  The roles of FPGAs in reprogrammable systems , 1998, Proc. IEEE.

[24]  Charles E. Leiserson,et al.  Retiming synchronous circuitry , 1988, Algorithmica.

[25]  Niraj K. Jha,et al.  Wavesched: a novel scheduling technique for control-flow intensive designs , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Heinrich Meyr,et al.  System level fixed-point design based on an interpolative approach , 1997, DAC.

[27]  Ian Page.  Constructing hardware-software systems from a single description , 1996, J. VLSI Signal Process..

[28]  Martin Radetzki.  Synthesis of digital circuits from object oriented specifications , 2000 .

[29]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[30]  Jonathan William Babb.  High level compilation for gate reconfigurable architectures , 2001 .

[31]  Delon Levi,et al.  JBits: Java based interface for reconfigurable computing , 1999 .

[32]  Peter M. Athanas,et al.  Quantitative analysis of floating point arithmetic on FPGA based custom computing machines , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[33]  Alok N. Choudhary,et al.  A system for synthesizing optimized FPGA hardware from Matlab(R) , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[34]  Margaret Martonosi,et al.  On Availability of Bit-Narrow Operations in General-Purpose Applications , 2000, FPL.

[35]  Seth Copen Goldstein,et al.  PipeRench: a co/processor for streaming multimedia acceleration , 1999, ISCA.

[36]  Rudy Lauwereins,et al.  DRESC: a retargetable compiler for coarse-grained reconfigurable architectures , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[37]  Chau-Wen Tseng,et al.  Data transformations for eliminating conflict misses , 1998, PLDI.

[38]  Alex K. Jones,et al.  A MATLAB compiler for distributed, heterogeneous, reconfigurable computing systems , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[39]  Paul Chow,et al.  Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation , 2000, CASES '00.

[40]  Peter M. Athanas,et al.  Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[41]  Dominique Lavenier,et al.  Fine grain parallelism on a MIMD machine using FPGAs , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[42]  Reiner W. Hartenstein,et al.  Parallelization in Co-Compilation for Configurable Accelerators. , 1998 .

[43]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[44]  Nikil D. Dutt,et al.  Speculation techniques for high level synthesis of control intensive designs , 2001, DAC '01.

[45]  Richard J. Carter,et al.  Attacking the semantic gap between application programming languages and configurable hardware , 2001, FPGA '01.

[46]  Maya Gokhale,et al.  Co-Synthesis to a Hybrid RISC/FPGA Architecture , 2000, J. VLSI Signal Process..

[47]  Gabriele Saucier,et al.  Using cone structures for circuit partitioning into FPGA packages , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[48]  Ranga Vemuri,et al.  Optimal temporal partitioning and synthesis for reconfigurable architectures , 1998, Proceedings Design, Automation and Test in Europe.

[49]  Eylon Caspi,et al.  Empirical Study of Opportunities for Bit-Level Specialization in , 2001 .

[50]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[51]  André DeHon,et al.  MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[52]  Margaret Martonosi,et al.  Dynamically exploiting narrow width operands to improve processor power and performance , 1999, Proceedings Fifth International Symposium on High-Performance Computer Architecture.

[53]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[54]  Steven S. Muchnick,et al.  Advanced Compiler Design and Implementation , 1997 .

[55]  Horácio C. Neto,et al.  An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs , 1999, VLSI.

[56]  Maya Gokhale,et al.  Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Arrays , 1995, FPL.

[57]  Kam-Wing Ng,et al.  A review of high-level synthesis for dynamically reconfigurable FPGAs , 2000, Microprocess. Microsystems.

[58]  Mary Sheeran,et al.  Lava: hardware design in Haskell , 1998, ICFP '98.

[59]  Rudy Lauwereins,et al.  ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.

[60]  Ranga Vemuri,et al.  Efficient resource arbitration in reconfigurable computing environments , 2000, DATE '00.

[61]  M AthanasPeter,et al.  Processor reconfiguration through instruction-set metamorphosis , 1993 .

[62]  K. Wakabayashi,et al.  A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[63]  Ranga Vemuri,et al.  An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[64]  Hiroyuki Tomiyama,et al.  Language and compiler for optimizing datapath widths of embedded systems , 1998 .

[65]  Pedro C. Diniz,et al.  Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[66]  John Wawrzynek,et al.  Fast module mapping and placement for datapaths in FPGAs , 1998, FPGA '98.

[67]  André DeHon,et al.  The Density Advantage of Configurable Computing , 2000, Computer.

[68]  Ranga Vemuri,et al.  Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints , 2000, IPDPS Workshops.

[69]  Mark Stephenson,et al.  Bidwidth analysis with application to silicon compilation , 2000, PLDI '00.

[70]  Pedro C. Diniz,et al.  Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[71]  Ranga Vemuri,et al.  Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[72]  S. Ghosh,et al.  An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[73]  Maya Gokhale,et al.  Stream-oriented FPGA computing in the Streams-C high level language , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[74]  Wolfgang Rosenstiel,et al.  New Algorithms, Architectures and Applications for Reconfigurable Computing , 2005 .

[75]  David R. Galloway.  The Transmogrifier C hardware description language and compiler for FPGAs , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[76]  Vivek Sarkar,et al.  Baring It All to Software: Raw Machines , 1997, Computer.

[77]  Pedro C. Diniz,et al.  Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[78]  Frank Vahid,et al.  Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance , 1998, TODE.

[79]  Rajesh Gupta,et al.  Hardware/software co-design , 1996, Proc. IEEE.

[80]  Alok N. Choudhary,et al.  Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[81]  Milind Girkar,et al.  Automatic Extraction of Functional Parallelism from Ordinary Programs , 1992, IEEE Trans. Parallel Distributed Syst..

[82]  Wayne Luk,et al.  Memory access optimisation for reconfigurable systems , 2001 .

[83]  B. Lin,et al.  Background memory management for dynamic data structure intensive processing systems , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[84]  Eduardo Sanchez,et al.  Spyder: a reconfigurable VLIW processor using FPGAs , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[85]  Seth Copen Goldstein,et al.  Efficient place and route for pipeline reconfigurable architectures , 2000, Proceedings 2000 International Conference on Computer Design.

[86]  Robert Rinker,et al.  An automated process for compiling dataflow graphs into reconfigurable hardware , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[87]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, ISCA '00.

[88]  Harvey F. Silverman,et al.  Processor reconfiguration through instruction-set metamorphosis , 1993, Computer.

[89]  Donald E. Thomas,et al.  Synthesis by Delayed Binding of Decisions , 1985, DAC 1985.

[90]  Niraj K. Jha,et al.  : a novel scheduling technique for control-flow intensive behavioral descriptions , 1997, ICCAD 1997.

[91]  Horácio C. Neto,et al.  Macro-based hardware compilation of Java/sup TM/ bytecodes into a dynamic reconfigurable computing system , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[92]  Seth Copen Goldstein,et al.  Fast compilation for pipelined reconfigurable fabrics , 1999, FPGA '99.

[93]  Gregory Allen.  Mitigation selection and qualification recommendations for Xilinx Virtex, Virtex-II, and Virtex-4 field programmable gate arrays , 2009 .

[94]  Bruce A. Draper,et al.  One-Step Compilation of Image Processing Applications to FPGAs , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[95]  Ranga Vemuri,et al.  An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures , 1998, IPPS/SPDP Workshops.

[96]  Giovanni De Micheli,et al.  Synthesis of hardware models in C with pointers and complex data structures , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[97]  Wayne Luk,et al.  Pipeline vectorization , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[98]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[99]  B. Ramakrishna Rau,et al.  Iterative modulo scheduling: an algorithm for software pipelining loops , 1994, MICRO 27.

[100]  Brad L. Hutchings,et al.  Sea Cucumber: A Synthesizing Compiler for FPGAs , 2002, FPL.

[101]  Rainer Kress,et al.  A fast reconfigurable ALU for Xputers , 1996 .

[102]  Miriam Leeser,et al.  High level synthesis for designing custom computing hardware , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[103]  Scott A. Mahlke,et al.  The program decision logic approach to predicated execution , 1999, ISCA.

[104]  John Wawrzynek,et al.  Instruction-Level Parallelism for Reconfigurable Computing , 1998, FPL.

[105]  Markus Weinhardt,et al.  XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture , 2002, FPL.

[106]  Kunle Olukotun,et al.  A quantitative analysis of reconfigurable coprocessors for multimedia applications , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[107]  Gabriele Saucier,et al.  Hierarchical Interactive Approach to Partition Large Designs into FPGAs , 1999, FPL.

[108]  Pedro C. Diniz,et al.  Bridging the Gap between Compilation and Synthesis in the DEFACTO System , 2001, LCPC.

[109]  Carl Ebeling,et al.  RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.

[110]  David Pellerin,et al.  Practical FPGA programming in C , 2005 .

[111]  Maya Gokhale,et al.  The NAPA adaptive processing architecture , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[112]  Frank Vahid.  Procedure exlining: a transformation for improved system and behavioral synthesis , 1995 .

[113]  Walid A. Najjar,et al.  A Compiler Intermediate Representation for Reconfigurable Fabrics , 2006, FPL.

[114]  Brad L. Hutchings,et al.  A dynamic instruction set computer , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[115]  John Wawrzynek,et al.  The Garp Architecture and C Compiler , 2000, Computer.

[116]  Maya Gokhale,et al.  Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays , 2005 .

[117]  Herman Schmit,et al.  Synthesis of application-specific memory designs , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[118]  Thomas L. Anderson,et al.  The cydra 5 minisupercomputer: Architecture and implementation , 1993, The Journal of Supercomputing.

[119]  Bjorn De Sutter,et al.  Hardware and a Tool Chain for ADRES , 2006, ARC.

[120]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[121]  Kazuyoshi Takagi,et al.  Hardware Synthesis from C Programs with Estimation of Bit Length of Variables , 1999 .

[122]  Walid A. Najjar,et al.  Input data reuse in compiling window operations onto reconfigurable hardware , 2004, LCTES '04.

[123]  Pedro C. Diniz,et al.  Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures , 2005, LCPC.

[124]  Michael Wolfe,et al.  High performance compilers for parallel computing , 1995 .

[125]  João M. P. Cardoso.  On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures , 2003, IEEE Trans. Computers.

[126]  John Wawrzynek,et al.  Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine , 2002, FPGA '02.

[127]  Brad L. Hutchings,et al.  Synthesizing RTL Hardware from Java Byte Codes , 2001, FPL.

[128]  共立出版株式会社.  コンピュータ・サイエンス : ACM computing surveys , 1978 .

[129]  Robert L. Bernstein.  Multiplication by integer constants , 1986, Softw. Pract. Exp..

[130]  Reiner W. Hartenstein,et al.  The microprocessor is no longer general purpose: why future reconfigurable platforms will win , 1997, 1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon.

[131]  Maya Gokhale,et al.  Trident: an FPGA compiler framework for floating-point algorithms , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[132]  Steven Trimberger,et al.  Scheduling designs into a time-multiplexed FPGA , 1998, FPGA '98.

[133]  Kevin E. Forward,et al.  Compiling to the gate level for a reconfigurable co-processor , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[134]  Walid A. Najjar,et al.  A Compiler Intermediate Representation for Reconfigurable Fabrics , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[135]  Stephen A. Edwards,et al.  High-Level Synthesis from the Synchronous Language Esterel , 2002, IWLS.

[136]  Reiner W. Hartenstein,et al.  A datapath synthesis system for the reconfigurable datapath architecture , 1995, ASP-DAC '95.

[137]  Rudy Lauwereins,et al.  Architecture exploration for a reconfigurable architecture template , 2005, IEEE Design & Test of Computers.

[138]  Kiran Bondalapati.  Parallelizing DSP nested loops on reconfigurable architectures using data context switching , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[139]  John Wawrzynek,et al.  Automatic compilation of c for hybrid reconfigurable architectures , 2002 .

[140]  Jonathan Rose,et al.  The Transmogrifier-2: a 1 million gate rapid prototyping system , 1997, FPGA '97.

[141]  Peter H. Bauer,et al.  Realization of block floating-point digital filters and application to block implementations , 1999, IEEE Trans. Signal Process..

[142]  Ken Kennedy,et al.  Conversion of control dependence to data dependence , 1983, POPL '83.

[143]  Peter Mark Athanas.  An adaptive machine architecture and compiler for dynamic processor reconfigurations , 1992 .

[144]  Pedro C. Diniz,et al.  Coarse-grain pipelining on multiple FPGA architectures , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[145]  Ricardo E. Gonzalez,et al.  Xtensa: A Configurable and Extensible Processor , 2000, IEEE Micro.

[146]  C. A. J. van Eijk,et al.  A code-motion pruning technique for global scheduling , 2000, TODE.

[147]  Dan Zuras,et al.  Integer multiplication and division on the HP Precision Architecture , 1987, ASPLOS 1987.

[148]  Peter Gray,et al.  An overview of the COBRA-ABS high level synthesis system for multi-FPGA systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[149]  Marco Platzner,et al.  Object-oriented domain specific compilers for programming FPGAs , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[150]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[151]  Seth Copen Goldstein,et al.  BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations , 2000, Euro-Par.

[152]  J. Ramanujam,et al.  Compile-Time Techniques for Data Distribution in Distributed Memory Machines , 1991, IEEE Trans. Parallel Distributed Syst..

[153]  Scott Mahlke,et al.  Effective compiler support for predicated execution using the hyperblock , 1992, MICRO 1992.

[154]  Dinesh Bhatia,et al.  Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers , 1999, IEEE Trans. Computers.

[155]  Dominique Lavenier,et al.  Evaluation of the streams-C C-to-FPGA compiler: an applications perspective , 2001, FPGA '01.

[156]  Herman Schmit,et al.  Address generation for memories containing multiple arrays , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[157]  Alok N. Choudhary,et al.  Parallelization of MATLAB Applications for a Multi-FPGA System , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[158]  Greg Snider.  Performance-constrained pipelining of software loops onto reconfigurable hardware , 2002, FPGA '02.

[159]  Viktor K. Prasanna,et al.  Dynamic precision management for loop computations on reconfigurable architectures , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[160]  Maya Gokhale,et al.  Automatic allocation of arrays to memories in FPGA processors with multiple memory banks , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[161]  Herman Schmit,et al.  Address generation for memories containing multiple arrays , 1995, ICCAD.

[162]  Richard J. Carter,et al.  Teramac-configurable custom computing , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[163]  Michael A. Langston,et al.  Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[164]  Jonathan Rose,et al.  The Transmogrifier-2: a 1 million gate rapid-prototyping system , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[165]  Mark Jones,et al.  Implementing an API for distributed adaptive computing systems , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[166]  Pheng-Ann Heng,et al.  Automatic floating to fixed point translation and its application to post-rendering 3D warping , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[167]  Niklaus Wirth.  Hardware Compilation: Translating Programs into Circuits , 1998, Computer.

[168]  R. Hartley.  Optimization of canonic signed digit multipliers for filter design , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[169]  Maya Gokhale,et al.  An introduction to compilation issues for parallel machines , 1992, The Journal of Supercomputing.

[170]  John J. Granacki,et al.  DEFACTO: A Design Environment for Adaptive Computing Technology , 1999, IPPS/SPDP Workshops.

[171]  John Wawrzynek,et al.  Stream Computations Organized for Reconfigurable Execution (SCORE) , 2000, FPL.

[172]  Jürgen Teich,et al.  Optimal FPGA module placement with temporal precedence constraints , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[173]  Ralph Wittig,et al.  OneChip: an FPGA processor with reconfigurable logic , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[174]  Jürgen Becker,et al.  High-performance computing using a reconfigurable accelerator , 1996, Concurr. Pract. Exp..

[175]  Ranga Vemuri,et al.  An integrated temporal partitioning and partial reconfiguration technique for design latency improvement , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[176]  Brad L. Hutchings,et al.  JHDL-an HDL for reconfigurable systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[177]  Viraphol Chaiyakul,et al.  An algorithm for array variable clustering , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[178]  Mark N. Wegman,et al.  Efficiently computing static single assignment form and the control dependence graph , 1991, TOPL.

[179]  Wayne Luk,et al.  Reconfigurable computing: architectures and design methods , 2005 .

[180]  Rahul Razdan,et al.  PRISC: programmable reduced instruction set computers , 1994 .

[181]  Russell Tessier,et al.  c ○ 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Reconfigurable Computing for Digital Signal Processing: A Survey ∗ , 1999 .

[182]  Milan Vasilko,et al.  Architectural Synthesis Techniques for Dynamically Reconfigurable Logic , 1996, FPL.

[183]  Tsutomu Maruyama,et al.  A C to HDL compiler for pipeline processing on FPGAs , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[184]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[185]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[186]  Stylianos Perissakis,et al.  Stream computations organized for reconfigurable execution , 2006, Microprocess. Microsystems.

[187]  Francky Catthoor,et al.  Background memory management for dynamic data structure intensive processing systems , 1995, ICCAD.

[188]  Scott A. Mahlke,et al.  Effective compiler support for predicated execution using the hyperblock , 1992, MICRO 25.

[189]  Niraj K. Jha,et al.  Memory binding for performance optimization of control-flow intensive behaviors , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[190]  Laurent Moll,et al.  High-Energy Physics on DECPeRLe-1 Programmable Active Memory , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[191]  J.M.P. Cardoso,et al.  Compilation for FPGA-based reconfigurable hardware , 2003, IEEE Design & Test of Computers.

[192]  Scott Hauck,et al.  The Chimaera reconfigurable functional unit , 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[193]  Peter Gray,et al.  The COBRA-ABS high-level synthesis system for multi-FPGA custom computing machines , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[194]  Csaba Andras Moritz,et al.  Parallelizing applications into silicon , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[195]  Daniel P. Lopresti,et al.  SPLASH: A Reconfigurable Linear Logic Array , 1990, ICPP.

[196]  Maya Gokhale,et al.  High level compilation for fine grained FPGAs , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[197]  Mary W. Hall,et al.  Increasing the Applicability of Scalar Replacement , 2004, CC.

[198]  Wayne Luk,et al.  Towards a declarative framework for hardware-software codesign , 1994, CODES.

[199]  Martin D. F. Wong,et al.  Circuit partitioning for dynamically reconfigurable FPGAs , 1999, FPGA '99.

[200]  Shiro Kobayashi,et al.  A software/hardware codesigned hands free system on a "resizable" block-floating-point DSP , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[201]  André DeHon,et al.  Reconfigurable architectures for general-purpose computing , 1996 .

[202]  Markus Weinhardt,et al.  PACT XPP—A Self-Reconfigurable Data Processing Architecture , 2003, The Journal of Supercomputing.

[203]  Edusmildo Orozco,et al.  Reconfigurable Computing. Accelerating Computation with Field-Programmable Gate Arrays , 2007, Scalable Comput. Pract. Exp..

[204]  Yanbing Li,et al.  Hardware-software co-design of embedded reconfigurable architectures , 2000, DAC.

[205]  Maya Gokhale,et al.  NAPA C: compiling for a hybrid RISC/FPGA architecture , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[206]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[207]  Prithviraj Banerjee,et al.  A C compiler for a processor with a reconfigurable functional unit , 2000, FPGA '00.

[208]  Steven W. K. Tjiang,et al.  SUIF: an infrastructure for research on parallelizing and optimizing compilers , 1994, SIGP.