A novel DS-CDMA RAKE receiver: architecture and performance

A DS-CDMA RAKE receiver architecture is proposed. Unlike the conventional receiver, the proposed /spl Sigma//spl Delta/-CDMA receiver does not require a /spl Sigma//spl Delta/ demodulator and a root-raised-cosine (RRC) filter, and hence its despreader can be implemented mainly using simple XNOR gates and 2-bit adders. The conditional BER for DS-CDMA forward link is derived and the averaged BER is obtained by Monte Carlo simulation. It is shown that the BER performance of the proposed receiver can match that of the conventional DS-CDMA receiver, which is implemented using a /spl Sigma//spl Delta/ analog-to-digital converter (ADC), with the proper choice of over-sampling ratio. And the proposed receiver achieves a much smaller gate-count than the conventional receiver when implemented on FPGA.