Frequent value encoding for low power data buses

Since the I/O pins of a CPU are a significant source of energy consumption, work has been done on developing encoding schemes for reducing switching activity on external buses. Modest reductions in switching can be achieved for data and address buses using a number of general purpose encoding schemes. However, by exploiting the characteristic of memory reference locality, switching activity on the address bus can be reduced by as much as 66%. Till now no characteristic has been identified that can be used to achieve similar reductions in switching activity on the data bus. We have discovered a characteristic of values transmitted over the data bus according to which a small number of distinct values, called frequent values, account for 32% of transmissions over the external data bus. Exploiting this characteristic we have developed an encoding scheme that we call the FV encoding scheme. To implement this scheme we have also developed a technique for dynamically identifying the frequent values which compares quite favorably with an optimal offline algorithm. Our experiments show that FV encoding of 32 frequent values yields an average reduction of 30% (with on-chip data cache) and 49% (without on-chip data cache) in data bus switching activity for SPEC95 and mediabench programs. Moreover the reduction in switching achieved by FV encoding is 2 to 4 times the reduction achieved by the bus-invert coding scheme and 1.5 to 3 times the reduction achieved by the adaptive method. The overall energy savings on data bus we attained considering the coder overhead is 29%.

[1]  Chi-Ying Tsui,et al.  Saving power in the control path of embedded processors , 1994, IEEE Design & Test of Computers.

[2]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Mircea R. Stan,et al.  Coding a terminated bus for low power , 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

[4]  Luca Benini,et al.  Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems , 1997, Proceedings Great Lakes Symposium on VLSI.

[5]  Tomás Lang,et al.  Exploiting the locality of memory references to reduce the address bus energy , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[6]  Naresh R. Shanbhag,et al.  A coding framework for low-power address and data busses , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Luca Benini,et al.  Synthesis of low-overhead interfaces for power-efficient communication over wide buses , 1999, DAC '99.

[8]  Frequent value locality and value-centric data cache design , 2000 .

[9]  César A. Piña The MOSIS Service , 2000 .

[10]  Jun Yang,et al.  Frequent value locality and value-centric data cache design , 2000, ASPLOS IX.

[11]  Taewhan Kim,et al.  Bus-invert coding for low-power I/O - a decomposition approach , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[12]  Naehyuck Chang,et al.  Bus encoding for low-power high-performance memory systems , 2000, DAC.

[13]  Wei-Chung Cheng,et al.  Power-optimal encoding for DRAM address bus (poster session) , 2000, ISLPED '00.

[14]  Wei-Chung Cheng,et al.  Power-optimal encoding for DRAM address bus , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[15]  Wei-Chung Cheng,et al.  Power-optimal encoding for a DRAM address bus , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Jun Yang,et al.  Frequent value locality and its applications , 2002, TECS.