Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors

We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency domain that is complete and self-consistent. It enables the manual design of frequency synthesis PLLs for loop bandwidth, output phase noise and minimum jitter. Tradeoffs between various parameters of the loop become clear. The analysis is validated against measurements on four very different loops, and helps to answer long-standing questions on aspects of these circuits attributable a hard nonlinearity. A brief designer’s guide is included.

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