A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 Simultaneous Wireless Inter-Tier Data and Power Transfer

This paper presents a 2-tier 3D-stacked Cortex-M0 SoC, in 65nm CMOS technology, with wireless inter-tier power and data transfer through an inductively coupled bus. The proposed design is the first implementation of a wireless link as part of a standard SoC bus, and achieves 20.3Gbps/mm2 data, and 7.1mW/mm2 power transfer simultaneously through a 250 μm channel. This also makes it the smallest ever reported inductive data and power link.