Algorithms for Taylor Expansion Diagrams.

The ever increasing size of integrated circuits results in large problem sizes during synthesis and verification of such designs. Recently Taylor Expansion Diagrams (TEDs) were introduced as a data structure to cope with large problem instances. TEDs allow to exploit high level information in the representation of functions. In this paper the basic TED operations are analyzed from a complexity point of view. Suggestions for optimizations of the originally proposed algorithms are made.

[1]  Fabio Somenzi,et al.  Efficient manipulation of decision diagrams , 2001, International Journal on Software Tools for Technology Transfer.

[2]  Massoud Pedram,et al.  Factored Edge-Valued Binary Decision Diagrams , 1997, Formal Methods Syst. Des..

[3]  Christoph Scholl,et al.  On WLCDs and the Complexity of Word-Level Decision Diagrams—A Lower Bound for Division , 2002, Formal Methods Syst. Des..

[4]  Zhihong Zeng,et al.  Taylor expansion diagrams: a compact, canonical representation with applications to symbolic verification , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[5]  Randal E. Bryant,et al.  Verification of arithmetic circuits using binary moment diagrams , 2001, International Journal on Software Tools for Technology Transfer.

[6]  Priyank Kalla,et al.  An infrastructure for rtl validation and verification , 2002 .

[7]  Rolf Drechsler,et al.  K*BMDs: a new data structure for verification , 1996, Proceedings ED&TC European Design and Test Conference.

[8]  Yung-Te Lai,et al.  Edge-valued binary decision diagrams for multi-level hierarchical verification , 1992, DAC '92.

[9]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[10]  Rolf Drechsler,et al.  Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams , 1994, 31st Design Automation Conference.

[11]  Priyank Kalla,et al.  High-level design verification using Taylor Expansion Diagrams: first results , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

[12]  Wolfgang Rosenstiel,et al.  Multilevel logic synthesis based on functional decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.

[13]  Bernd Becker,et al.  Fast OFDD based minimization of fixed polarity Reed-Muller expressions , 1994, EURO-DAC '94.

[14]  Rolf Drechsler,et al.  On the representational power of bit-level and word-level decision diagrams , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[15]  R. Bryant,et al.  Verification of Arithmetic Functions with Binary Moment Diagrams , 1994 .